Hi Maxime
On Wed, 8 Jul 2020 at 18:43, Maxime Ripard <maxime@xxxxxxxxxx> wrote:
>
> On BCM2711 to avoid stale pixels getting stuck in intermediate FIFOs, the
> pixelvalve needs to be setup each time there's a mode change or enable /
> disable sequence.
>
> Therefore, we can't really use mode_set_nofb anymore to configure it, but
> we need to move it to atomic_enable.
>
> Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx>
Reviewed-by: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/vc4/vc4_crtc.c | 7 +------
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
> index 284a85b9d7d4..2eda2e6429ec 100644
> --- a/drivers/gpu/drm/vc4/vc4_crtc.c
> +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
> @@ -376,11 +376,6 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
> }
> }
>
> -static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
> -{
> - vc4_crtc_config_pv(crtc);
> -}
> -
> static void require_hvs_enabled(struct drm_device *dev)
> {
> struct vc4_dev *vc4 = to_vc4_dev(dev);
> @@ -433,6 +428,7 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
> require_hvs_enabled(dev);
>
> vc4_crtc_pixelvalve_reset(crtc);
> + vc4_crtc_config_pv(crtc);
>
> CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
>
> @@ -791,7 +787,6 @@ static const struct drm_crtc_funcs vc4_crtc_funcs = {
> };
>
> static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
> - .mode_set_nofb = vc4_crtc_mode_set_nofb,
> .mode_valid = vc4_crtc_mode_valid,
> .atomic_check = vc4_crtc_atomic_check,
> .atomic_flush = vc4_hvs_atomic_flush,
> --
> git-series 0.9.1
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