Hi Maxime On Wed, 8 Jul 2020 at 18:42, Maxime Ripard <maxime@xxxxxxxxxx> wrote: > > The VIDEN bit in the pixelvalve currently being used to enable or disable > the pixelvalve seems to not be enough in some situations, which whill end > up with the pixelvalve stalling. > > In such a case, even re-enabling VIDEN doesn't bring it back and we need to > clear the FIFO. This can only be done if the pixelvalve is disabled though. > > In order to overcome this, we can configure the pixelvalve during > mode_set_no_fb, but only enable it in atomic_enable and flush the FIFO > there, and in atomic_disable disable the pixelvalve again. Very minor nitpick: the configure is in vc4_crtc_config_pv, but that is called from mode_set_no_fb. The comment is correct from a DRM overview perspective, but not from the actual code. Describing the DRM call is probably the better approach, but it looks odd when compared to the code. > Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx> Reviewed-by: Dave Stevenson <dave.stevenson@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/vc4/vc4_crtc.c | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c > index cdeaa0cd981f..fe2e5675aed4 100644 > --- a/drivers/gpu/drm/vc4/vc4_crtc.c > +++ b/drivers/gpu/drm/vc4/vc4_crtc.c > @@ -332,9 +332,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc) > PV_CONTROL_TRIGGER_UNDERFLOW | > PV_CONTROL_WAIT_HSTART | > VC4_SET_FIELD(vc4_encoder->clock_select, > - PV_CONTROL_CLK_SELECT) | > - PV_CONTROL_FIFO_CLR | > - PV_CONTROL_EN); > + PV_CONTROL_CLK_SELECT)); > } > > static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) > @@ -386,6 +384,8 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, > ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); > WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); > > + CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN); > + > vc4_hvs_atomic_disable(crtc, old_state); > > /* > @@ -410,6 +410,10 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, > > require_hvs_enabled(dev); > > + /* Reset the PV fifo. */ > + CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | > + PV_CONTROL_FIFO_CLR | PV_CONTROL_EN); > + > /* Enable vblank irq handling before crtc is started otherwise > * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist(). > */ > -- > git-series 0.9.1 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
