[radeon-alex:amd-staging-drm-next 628/1015] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c:268:17: sparse: sparse: cast removes address space '<asn:1>' of expression

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tree:   git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next
head:   3c831e196bd7543977d4acd506064636809f1dcf
commit: 10be8791067fc672e44fcaa7afb886390909a0c0 [628/1015] drm/amdkfd: Support Sienna_Cichlid KFD v4
config: x86_64-randconfig-s022-20200710 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-14) 9.3.0
reproduce:
        # apt-get install sparse
        # sparse version: v0.6.2-37-gc9676a3b-dirty
        git checkout 10be8791067fc672e44fcaa7afb886390909a0c0
        # save the attached .config to linux build tree
        make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>


sparse warnings: (new ones prefixed by >>)

>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c:268:17: sparse: sparse: cast removes address space '<asn:1>' of expression
   drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c:270:17: sparse: sparse: cast removes address space '<asn:1>' of expression

vim +268 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

   192	
   193	static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
   194				uint32_t queue_id, uint32_t __user *wptr,
   195				uint32_t wptr_shift, uint32_t wptr_mask,
   196				struct mm_struct *mm)
   197	{
   198		struct amdgpu_device *adev = get_amdgpu_device(kgd);
   199		struct v10_compute_mqd *m;
   200		uint32_t *mqd_hqd;
   201		uint32_t reg, hqd_base, data;
   202	
   203		m = get_mqd(mqd);
   204	
   205		pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id);
   206		acquire_queue(kgd, pipe_id, queue_id);
   207	
   208		/* HIQ is set during driver init period with vmid set to 0*/
   209		if (m->cp_hqd_vmid == 0) {
   210			uint32_t value, mec, pipe;
   211	
   212			mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
   213			pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
   214	
   215			pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
   216				mec, pipe, queue_id);
   217			value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));
   218			value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
   219				((mec << 5) | (pipe << 3) | queue_id | 0x80));
   220			WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value);
   221		}
   222	
   223		/* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
   224		mqd_hqd = &m->cp_mqd_base_addr_lo;
   225		hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
   226	
   227		for (reg = hqd_base;
   228		     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
   229			WREG32(reg, mqd_hqd[reg - hqd_base]);
   230	
   231	
   232		/* Activate doorbell logic before triggering WPTR poll. */
   233		data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
   234				     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
   235		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
   236	
   237		if (wptr) {
   238			/* Don't read wptr with get_user because the user
   239			 * context may not be accessible (if this function
   240			 * runs in a work queue). Instead trigger a one-shot
   241			 * polling read from memory in the CP. This assumes
   242			 * that wptr is GPU-accessible in the queue's VMID via
   243			 * ATC or SVM. WPTR==RPTR before starting the poll so
   244			 * the CP starts fetching new commands from the right
   245			 * place.
   246			 *
   247			 * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit
   248			 * tricky. Assume that the queue didn't overflow. The
   249			 * number of valid bits in the 32-bit RPTR depends on
   250			 * the queue size. The remaining bits are taken from
   251			 * the saved 64-bit WPTR. If the WPTR wrapped, add the
   252			 * queue size.
   253			 */
   254			uint32_t queue_size =
   255				2 << REG_GET_FIELD(m->cp_hqd_pq_control,
   256						   CP_HQD_PQ_CONTROL, QUEUE_SIZE);
   257			uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1);
   258	
   259			if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr)
   260				guessed_wptr += queue_size;
   261			guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
   262			guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
   263	
   264			WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
   265			       lower_32_bits(guessed_wptr));
   266			WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
   267			       upper_32_bits(guessed_wptr));
 > 268			WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
   269			       lower_32_bits((uint64_t)wptr));
   270			WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
   271			       upper_32_bits((uint64_t)wptr));
   272			pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
   273				 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
   274			WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
   275			       (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
   276		}
   277	
   278		/* Start the EOP fetcher */
   279		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
   280		       REG_SET_FIELD(m->cp_hqd_eop_rptr,
   281				     CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
   282	
   283		data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
   284		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
   285	
   286		release_queue(kgd);
   287	
   288		return 0;
   289	}
   290	

---
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