On Sun, Jun 07, 2020 at 08:18:29PM +0200, Hans de Goede wrote: > According to the data-sheet the way the PWM controller works is that > each input clock-cycle the base_unit gets added to a N bit counter and > that counter overflowing determines the PWM output frequency. > > So assuming e.g. a 16 bit counter this means that if base_unit is set to 1, > after 65535 input clock-cycles the counter has been increased from 0 to > 65535 and it will overflow on the next cycle, so it will overflow after > every 65536 clock cycles and thus the calculations done in > pwm_lpss_prepare() should use 65536 and not 65535. > > This commit fixes this. Note this also aligns the calculations in > pwm_lpss_prepare() with those in pwm_lpss_get_state(). This one sounds like a bug which I have noticed on Broxton (but thought as a hardware issue). In any case it has to be tested on various platforms to see how it affects on them. -- With Best Regards, Andy Shevchenko _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
