Hi Doug. On Mon, Jun 01, 2020 at 05:30:53PM -0700, Doug Anderson wrote: > Hi, > > On Mon, Jun 1, 2020 at 1:33 AM Sam Ravnborg <sam@xxxxxxxxxxxx> wrote: > > > > This panel is used on evaluation boards for Atmel at91sam9261 and > > at91sam6263. > > > > Signed-off-by: Sam Ravnborg <sam@xxxxxxxxxxxx> > > Cc: Thierry Reding <thierry.reding@xxxxxxxxx> > > Cc: Sam Ravnborg <sam@xxxxxxxxxxxx> > > --- > > drivers/gpu/drm/panel/panel-simple.c | 29 ++++++++++++++++++++++++++++ > > 1 file changed, 29 insertions(+) > > > > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c > > index 8624bb80108c..25c96639631f 100644 > > --- a/drivers/gpu/drm/panel/panel-simple.c > > +++ b/drivers/gpu/drm/panel/panel-simple.c > > @@ -1813,6 +1813,32 @@ static const struct panel_desc hannstar_hsd100pxn1 = { > > .connector_type = DRM_MODE_CONNECTOR_LVDS, > > }; > > > > +static const struct drm_display_mode hitachi_tx09d71vm1cca_mode = { > > + .clock = 4965000, > > This is the pixel clock in kHz, right? So it runs at almost 5 Terahertz? > > > > + .hdisplay = 240, > > + .hsync_start = 240 + 0, > > + .hsync_end = 240 + 0 + 5, > > + .htotal = 240 + 0 + 5 + 1, > > + .vdisplay = 320, > > + .vsync_start = 320 + 0, > > + .vsync_end = 320 + 0 + 1, > > + .vtotal = 320 + 0 + 1 + 1, > > Some random datasheet I found has really different numbers. If the > numbers above are what everyone is using then I suppose it's fine, > just curious why the mismatch. The timing comes from: arch/arm/boot/dts/at91sam9263ek.dts - that include display timings for the panel on the evaluation board. I did not verify any datasheet - I just blindly copied what was there. And clock was obviously not properly adjusted to khz. Will fix in v2 - will also try to find a datasheet this time. Thanks for noticing! Sam _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel