On Mon, May 11, 2020 at 5:42 PM Alex Deucher <alexdeucher@xxxxxxxxx> wrote: > > On Mon, May 11, 2020 at 3:18 AM Paul Menzel <pmenzel@xxxxxxxxxxxxx> wrote: > > > > Fix all occurrences with the commands below. > > > > $ git grep -l equnce drivers/gpu/ | xargs sed -i 's/equnce/equence/g' > > > > Cc: Alex Deucher <alexander.deucher@xxxxxxx> > > Cc: Christian König <christian.koenig@xxxxxxx> > > Cc: David (ChunMing) Zhou <David1.Zhou@xxxxxxx> > > Cc: amd-gfx@xxxxxxxxxxxxxxxxxxxxx > > Signed-off-by: Paul Menzel <pmenzel@xxxxxxxxxxxxx> > > Please split these up per driver. Also, historically we haven't > changed atombios.h since it's shared across OSes, but I guess at this > point it's legacy since we are using atomfirmware.h for newer parts. Same comment on the other patches. Alex > > Alex > > > --- > > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- > > drivers/gpu/drm/amd/include/atombios.h | 6 +++--- > > drivers/gpu/drm/radeon/atombios.h | 6 +++--- > > drivers/gpu/drm/radeon/cik.c | 4 ++-- > > drivers/gpu/drm/radeon/radeon_fence.c | 6 +++--- > > 5 files changed, 13 insertions(+), 13 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > index 733d398c61ccb..3da40056c6c5d 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > @@ -2176,7 +2176,7 @@ static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) > > * @adev: amdgpu_device pointer > > * @fence: amdgpu fence object > > * > > - * Emits a fence sequnce number on the gfx ring and flushes > > + * Emits a fence sequence number on the gfx ring and flushes > > * GPU caches. > > */ > > static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, > > @@ -2217,7 +2217,7 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, > > * @adev: amdgpu_device pointer > > * @fence: amdgpu fence object > > * > > - * Emits a fence sequnce number on the compute ring and flushes > > + * Emits a fence sequence number on the compute ring and flushes > > * GPU caches. > > */ > > static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, > > diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h > > index 8ba21747b40a3..afef574c3b88b 100644 > > --- a/drivers/gpu/drm/amd/include/atombios.h > > +++ b/drivers/gpu/drm/amd/include/atombios.h > > @@ -6138,7 +6138,7 @@ ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. > > > > ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. > > > > -ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. > > +ulNbpStateMemclkFreq[4]: system memory clock frequencey in unit of 10Khz in different NB pstate. > > > > **********************************************************************************************************************/ > > > > @@ -6346,7 +6346,7 @@ ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is custom > > > > ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL > > > > -ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). > > +ulNbpStateMemclkFreq[4]: system memory clock frequencey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). > > ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State > > usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage > > usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded > > @@ -8902,7 +8902,7 @@ typedef struct _ATOM_XTMDS_INFO > > ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip > > UCHAR ucXtransimitterID; > > UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported > > - UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters > > + UCHAR ucSequenceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters > > // due to design. This ID is used to alert driver that the sequence is not "standard"! > > UCHAR ucMasterAddress; // Address to control Master xTMDS Chip > > UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip > > diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h > > index 4b86e8b450090..4d0f6de32957f 100644 > > --- a/drivers/gpu/drm/radeon/atombios.h > > +++ b/drivers/gpu/drm/radeon/atombios.h > > @@ -5206,7 +5206,7 @@ ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. > > > > ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. > > > > -ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. > > +ulNbpStateMemclkFreq[4]: system memory clock frequencey in unit of 10Khz in different NB pstate. > > > > **********************************************************************************************************************/ > > > > @@ -5413,7 +5413,7 @@ ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is custom > > > > ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL > > > > -ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). > > +ulNbpStateMemclkFreq[4]: system memory clock frequencey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). > > ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State > > usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage > > usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded > > @@ -7597,7 +7597,7 @@ typedef struct _ATOM_XTMDS_INFO > > ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip > > UCHAR ucXtransimitterID; > > UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported > > - UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters > > + UCHAR ucSequenceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters > > // due to design. This ID is used to alert driver that the sequence is not "standard"! > > UCHAR ucMasterAddress; // Address to control Master xTMDS Chip > > UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip > > diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c > > index 5c42877fd6fbf..4ce70793e85fb 100644 > > --- a/drivers/gpu/drm/radeon/cik.c > > +++ b/drivers/gpu/drm/radeon/cik.c > > @@ -3544,7 +3544,7 @@ static void cik_hdp_flush_cp_ring_emit(struct radeon_device *rdev, > > * @rdev: radeon_device pointer > > * @fence: radeon fence object > > * > > - * Emits a fence sequnce number on the gfx ring and flushes > > + * Emits a fence sequence number on the gfx ring and flushes > > * GPU caches. > > */ > > void cik_fence_gfx_ring_emit(struct radeon_device *rdev, > > @@ -3585,7 +3585,7 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev, > > * @rdev: radeon_device pointer > > * @fence: radeon fence object > > * > > - * Emits a fence sequnce number on the compute ring and flushes > > + * Emits a fence sequence number on the compute ring and flushes > > * GPU caches. > > */ > > void cik_fence_compute_ring_emit(struct radeon_device *rdev, > > diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c > > index 43f2f93078668..77658ecdd181b 100644 > > --- a/drivers/gpu/drm/radeon/radeon_fence.c > > +++ b/drivers/gpu/drm/radeon/radeon_fence.c > > @@ -338,7 +338,7 @@ void radeon_fence_process(struct radeon_device *rdev, int ring) > > * @seq: sequence number > > * @ring: ring index the fence is associated with > > * > > - * Check if the last signaled fence sequnce number is >= the requested > > + * Check if the last signaled fence sequence number is >= the requested > > * sequence number (all asics). > > * Returns true if the fence has signaled (current fence value > > * is >= requested value) or false if it has not (current fence > > @@ -458,7 +458,7 @@ bool radeon_fence_signaled(struct radeon_fence *fence) > > * @rdev: radeon device pointer > > * @seq: sequence numbers > > * > > - * Check if the last signaled fence sequnce number is >= the requested > > + * Check if the last signaled fence sequence number is >= the requested > > * sequence number (all asics). > > * Returns true if any has signaled (current value is >= requested value) > > * or false if it has not. Helper function for radeon_fence_wait_seq. > > @@ -483,7 +483,7 @@ static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq) > > * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait > > * > > * Wait for the requested sequence number(s) to be written by any ring > > - * (all asics). Sequnce number array is indexed by ring id. > > + * (all asics). Sequence number array is indexed by ring id. > > * @intr selects whether to use interruptable (true) or non-interruptable > > * (false) sleep when waiting for the sequence number. Helper function > > * for radeon_fence_wait_*(). > > -- > > 2.26.2 > > > > _______________________________________________ > > dri-devel mailing list > > dri-devel@xxxxxxxxxxxxxxxxxxxxx > > https://lists.freedesktop.org/mailman/listinfo/dri-devel _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
