Hi Neil, On Tue, Apr 28, 2020 at 11:21 AM Neil Armstrong <narmstrong@xxxxxxxxxxxx> wrote: > > The Amlogic S805X/Y uses the same die as the S905X, but with more > limited graphics capabilities. > > This adds a soc version detection adding specific limitations on the HDMI > mode selections. > > Here, we limit to HDMI 1.3a max HDMI PHY clock frequency. for my own education: 1.65GHz from the PLL will be divided down to 165MHz isn't this more like the limit of HDMI 1.2a? > Changes sinces v1: > - Moved frequency check in the vclk code, and also checks DMT modes > > Signed-off-by: Neil Armstrong <narmstrong@xxxxxxxxxxxx> Acked-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> This looks good to me based on the current limitations of meson_vclk.c If we switch to CCF based VPU clock rate changes then we should do this in the clock driver by calling clk_hw_set_rate_range(hdmi_pll, 0, 1.65GHz) The good thing is: we can re-use struct meson_drm_soc_limits even after switching to CCF. We will just need to set the max PHY freq using clk_round_rate(hdmi_pll, ULONG_MAX) Martin _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
