> -----Original Message-----
> From: Jani Nikula <jani.nikula@xxxxxxxxx>
> Sent: Friday, March 27, 2020 6:12 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; dri-devel@xxxxxxxxxxxxxxxxxxxxx
> Cc: Nikula, Jani <jani.nikula@xxxxxxxxx>; Navare, Manasi D
> <manasi.d.navare@xxxxxxxxx>; Kulkarni, Vandita <vandita.kulkarni@xxxxxxxxx>
> Subject: [PATCH RESEND 4/7] drm/i915/dsc: configure hardware using
> specified rc_model_size
>
> The rc_model_size is specified in the DSC config, and the hardware
> programming should respect that instead of hard coding a value of 8192.
>
> Regardless, the rc_model_size in DSC config is currently hard coded to the
> same value, so this should have no impact, other than allowing the use of other
> sizes as needed.
>
> Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> Cc: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 95ad87d4ccb3..1f74b0174b1a 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -740,7 +740,7 @@ static void intel_dsc_pps_configure(struct
> intel_encoder *encoder,
>
> /* Populate PICTURE_PARAMETER_SET_9 registers */
> pps_val = 0;
> - pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
> + pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
> DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
> drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
> if (!is_pipe_dsc(crtc_state)) {
> --
> 2.20.1
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