Setup the Amlogic FBC decoder for the VD1 video overlay plane to use
read the FBC header as Scatter Memory layout reference.
Tested-by: Kevin Hilman <khilman@xxxxxxxxxxxx>
Signed-off-by: Neil Armstrong <narmstrong@xxxxxxxxxxxx>
---
drivers/gpu/drm/meson/meson_overlay.c | 48 +++++++++++++++++----------
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/meson_overlay.c
index 8b9d4984b2a7..3c54135f53a0 100644
--- a/drivers/gpu/drm/meson/meson_overlay.c
+++ b/drivers/gpu/drm/meson/meson_overlay.c
@@ -487,6 +487,9 @@ static void meson_overlay_atomic_update(struct drm_plane *plane,
AFBC_HOLD_LINE_NUM(8) |
AFBC_BURST_LEN(2);
+ if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC_LAYOUT_SCATTER)
+ priv->viu.vd1_afbc_mode |= AFBC_SCATTER_MODE;
+
if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC_MEM_SAVING)
priv->viu.vd1_afbc_mode |= AFBC_BLK_MEM_MODE;
@@ -675,23 +678,32 @@ static void meson_overlay_atomic_update(struct drm_plane *plane,
}
if (priv->viu.vd1_afbc) {
- /* Default mode is 4k per superblock */
- unsigned long block_size = 4096;
- unsigned long body_size;
-
- /* 8bit mem saving mode is 3072bytes per superblock */
- if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE)
- block_size = 3072;
-
- body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) *
- (ALIGN(priv->viu.vd1_height0, 32) / 32) *
- block_size;
-
- priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4;
-
- /* Header is after body content */
- priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 +
- body_size) >> 4;
+ if (priv->viu.vd1_afbc_mode & AFBC_SCATTER_MODE) {
+ /*
+ * In Scatter mode, the header contains the physical
+ * body content layout, thus the body content
+ * size isn't needed.
+ */
+ priv->viu.vd1_afbc_head_addr = priv->viu.vd1_addr0 >> 4;
+ priv->viu.vd1_afbc_body_addr = 0;
+ } else {
+ /* Default mode is 4k per superblock */
+ unsigned long block_size = 4096;
+ unsigned long body_size;
+
+ /* 8bit mem saving mode is 3072bytes per superblock */
+ if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE)
+ block_size = 3072;
+
+ body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) *
+ (ALIGN(priv->viu.vd1_height0, 32) / 32) *
+ block_size;
+
+ priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4;
+ /* Header is after body content */
+ priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 +
+ body_size) >> 4;
+ }
}
priv->viu.vd1_enabled = true;
@@ -771,6 +783,8 @@ static const uint32_t supported_drm_formats[] = {
};
static const uint64_t format_modifiers[] = {
+ DRM_FORMAT_MOD_AMLOGIC_FBC(DRM_FORMAT_MOD_AMLOGIC_FBC_LAYOUT_SCATTER |
+ DRM_FORMAT_MOD_AMLOGIC_FBC_MEM_SAVING),
DRM_FORMAT_MOD_AMLOGIC_FBC(DRM_FORMAT_MOD_AMLOGIC_FBC_LAYOUT_BASIC |
DRM_FORMAT_MOD_AMLOGIC_FBC_MEM_SAVING),
DRM_FORMAT_MOD_AMLOGIC_FBC(DRM_FORMAT_MOD_AMLOGIC_FBC_LAYOUT_BASIC),
--
2.22.0
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