On 2020-03-17 6:21 p.m., Lucas Stach wrote: > That's one of the issues with implicit sync that explicit may solve: > a single client taking way too much time to render something can > block the whole pipeline up until the display flip. With explicit > sync the compositor can just decide to use the last client buffer if > the latest buffer isn't ready by some deadline. FWIW, the compositor can do this with implicit sync as well, by polling a dma-buf fd for the buffer. (Currently, it has to poll for writable, because waiting for the exclusive fence only isn't enough with amdgpu) -- Earthling Michel Dänzer | https://redhat.com Libre software enthusiast | Mesa and X developer _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
