Neil Armstrong <narmstrong@xxxxxxxxxxxx> writes: > Amlogic uses a proprietary lossless image compression protocol and format > for their hardware video codec accelerators, either video decoders or > video input encoders. > > It considerably reduces memory bandwidth while writing and reading > frames in memory. > > The underlying storage is considered to be 3 components, 8bit or 10-bit > per component, YCbCr 420, single plane : > - DRM_FORMAT_YUV420_8BIT > - DRM_FORMAT_YUV420_10BIT > > This modifier will be notably added to DMA-BUF frames imported from the V4L2 > Amlogic VDEC decoder. > > At least two options are supported : > - Scatter mode: the buffer is filled with a IOMMU scatter table referring > to the encoder current memory layout. This mode if more efficient in terms > of memory allocation but frames are not dumpable and only valid during until > the buffer is freed and back in control of the encoder > - Memory saving: when the pixel bpp is 8b, the size of the superblock can > be reduced, thus saving memory. > > This serie adds the missing register, updated the FBC decoder registers > content to be committed by the crtc code. > > The Amlogic FBC has been tested with compressed content from the Amlogic > HW VP9 decoder on S905X (GXL), S905D2 (G12A) and S905X3 (SM1) in 8bit > (Scatter+Mem Saving on G12A/SM1, Mem Saving on GXL) and 10bit > (Scatter on G12A/SM1, default on GXL). > > It's expected to work as-is on GXM and G12B SoCs. Tested on meson-sm1-sei610 with 4k@60p (VP9) streams. Tested-by: Kevin Hilman <khilman@xxxxxxxxxxxx> Kevin _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
