On Thu, Dec 19, 2019 at 5:20 PM Maxime Ripard <maxime@xxxxxxxxxx> wrote:
>
> The DRC needs to run at 300MHz to be functional. This was done so far
> using assigned-clocks in the device tree, but that is easy to forget, and
> dosen't provide any other guarantee than the rate is going to be roughly
> the one requested at probe time.
>
> Therefore it's pretty fragile, so let's just use the exclusive clock API to
> enforce it.
>
> Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx>
> ---
> drivers/gpu/drm/sun4i/sun6i_drc.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/sun4i/sun6i_drc.c b/drivers/gpu/drm/sun4i/sun6i_drc.c
> index f7ab72244796..ddb52da90103 100644
> --- a/drivers/gpu/drm/sun4i/sun6i_drc.c
> +++ b/drivers/gpu/drm/sun4i/sun6i_drc.c
> @@ -57,6 +57,7 @@ static int sun6i_drc_bind(struct device *dev, struct device *master,
> goto err_disable_bus_clk;
> }
> clk_prepare_enable(drc->mod_clk);
> + clk_set_rate_exclusive(drc->mod_clk, 300000000);
I wonder what would happen if this fails...
>
> return 0;
>
> @@ -72,6 +73,7 @@ static void sun6i_drc_unbind(struct device *dev, struct device *master,
> {
> struct sun6i_drc *drc = dev_get_drvdata(dev);
>
> + clk_rate_exclusive_put(drc->mod_clk);
and we try to do the put regardless...
ChenYu
> clk_disable_unprepare(drc->mod_clk);
> clk_disable_unprepare(drc->bus_clk);
> reset_control_assert(drc->reset);
> --
> 2.23.0
>
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