Hi Maxime,
Maxime Ripard <maxime@xxxxxxxxxx> wrote on Mon, 16 Dec 2019 11:58:27
+0100:
> Hi,
>
> On Fri, Dec 13, 2019 at 07:10:48PM +0100, Miquel Raynal wrote:
> > +static int px30_lvds_grf_config(struct drm_encoder *encoder,
> > + struct drm_display_mode *mode)
> > +{
> > + struct rockchip_lvds *lvds = encoder_to_lvds(encoder);
> > + u8 nhsync = !(mode->flags & DRM_MODE_FLAG_PHSYNC);
> > + u8 nvsync = !(mode->flags & DRM_MODE_FLAG_PVSYNC);
> > + u8 ndclk = !(mode->flags & DRM_MODE_FLAG_PCSYNC);
> > + int ret;
> > +
> > + if (lvds->output != DISPLAY_OUTPUT_LVDS) {
> > + DRM_DEV_ERROR(lvds->dev, "Unsupported display output %d\n",
> > + lvds->output);
> > + return -EINVAL;
> > + }
> > +
> > + if (nhsync ^ nvsync) {
> > + DRM_DEV_ERROR(lvds->dev, "Unsupported Hsync/Vsync polarity\n");
> > + return -EINVAL;
> > + }
> > +
> > + /* Set format */
> > + ret = regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON1,
> > + PX30_LVDS_FORMAT(lvds->format),
> > + PX30_LVDS_FORMAT(lvds->format));
> > + if (ret)
> > + return ret;
> > +
> > + /* Control Hsync/Vsync polarity */
> > + ret = regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON0,
> > + PX30_LVDS_TIE_CLKS(1),
> > + PX30_LVDS_TIE_CLKS(1));
> > + if (ret)
> > + return ret;
> > +
> > + /* Set Hsync/Vsync polarity */
> > + ret = regmap_update_bits(lvds->grf, PX30_LVDS_GRF_PD_VO_CON0,
> > + PX30_LVDS_INVERT_CLKS(1),
> > + PX30_LVDS_INVERT_CLKS(nhsync));
> > + if (ret)
> > + return ret;
>
> I don't know the hardware but it seems pretty weird to me. hsync and
> vsync in LVDS are not clocks (or even signals), they're a bit in the
> payload. Is there any explanation in the datasheet (or even a
> datasheet in the first place)?
There is no explanation about this in the PX30 TRM part 1 (public). But
you are right the naming is weird. Could the "tie clocks" thing above
mean something to you/people knowing the LVDS world?
Cheers,
Miquèl
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