Hi,
> -----Original Message-----
> From: Kishon Vijay Abraham I <kishon@xxxxxx>
> Sent: Monday, December 9, 2019 14:21
> To: Yuti Suresh Amonkar <yamonkar@xxxxxxxxxxx>; dri-
> devel@xxxxxxxxxxxxxxxxxxxxx; Rob Herring <robh+dt@xxxxxxxxxx>
> Cc: jsarha@xxxxxx; tomi.valkeinen@xxxxxx; praneeth@xxxxxx; Milind Parab
> <mparab@xxxxxxxxxxx>; Dhananjay Vilasrao Kangude
> <dkangude@xxxxxxxxxxx>; Swapnil Kashinath Jakhade
> <sjakhade@xxxxxxxxxxx>
> Subject: Re: [PATCH v1 02/15] dt-bindings:phy: Convert Cadence MHDP PHY
> bindings to YAML.
>
> EXTERNAL MAIL
>
>
> +Rob
>
>
>
> Hi,
>
>
>
> On 03/12/19 3:43 pm, Yuti Amonkar wrote:
>
> > - Convert the MHDP PHY devicetree bindings to yaml schemas.
>
> > - Rename DP PHY to have generic Torrent PHY nomrnclature.
>
> > - Rename compatible string from "cdns,dp-phy" to "cdns,torrent-phy".
>
> >
>
> > Signed-off-by: Yuti Amonkar <yamonkar@xxxxxxxxxxx>
>
> > ---
>
> > .../devicetree/bindings/phy/phy-cadence-dp.txt | 30 -------------
>
> > .../bindings/phy/phy-cadence-torrent.yaml | 52
> ++++++++++++++++++++++
>
> > 2 files changed, 52 insertions(+), 30 deletions(-)
>
> > delete mode 100644 Documentation/devicetree/bindings/phy/phy-
> cadence-dp.txt
>
> > create mode 100644 Documentation/devicetree/bindings/phy/phy-
> cadence-torrent.yaml
>
> >
>
> > diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
> b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
>
> > deleted file mode 100644
>
> > index 7f49fd54e..0000000
>
> > --- a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
>
> > +++ /dev/null
>
> > @@ -1,30 +0,0 @@
>
> > -Cadence MHDP DisplayPort SD0801 PHY binding
>
> > -===========================================
>
> > -
>
> > -This binding describes the Cadence SD0801 PHY hardware included with
>
> > -the Cadence MHDP DisplayPort controller.
>
> > -
>
> > --------------------------------------------------------------------------------
>
> > -Required properties (controller (parent) node):
>
> > -- compatible : Should be "cdns,dp-phy"
>
> > -- reg : Defines the following sets of registers in the parent
>
> > - mhdp device:
>
> > - - Offset of the DPTX PHY configuration registers
>
> > - - Offset of the SD0801 PHY configuration registers
>
> > -- #phy-cells : from the generic PHY bindings, must be 0.
>
> > -
>
> > -Optional properties:
>
> > -- num_lanes : Number of DisplayPort lanes to use (1, 2 or 4)
>
> > -- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps
> (2160,
>
> > - 2430, 2700, 3240, 4320, 5400 or 8100)
>
> > --------------------------------------------------------------------------------
>
> > -
>
> > -Example:
>
> > - dp_phy: phy@f0fb030a00 {
>
> > - compatible = "cdns,dp-phy";
>
> > - reg = <0xf0 0xfb030a00 0x0 0x00000040>,
>
> > - <0xf0 0xfb500000 0x0 0x00100000>;
>
> > - num_lanes = <4>;
>
> > - max_bit_rate = <8100>;
>
> > - #phy-cells = <0>;
>
> > - };
>
> > diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-
> torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-
> torrent.yaml
>
> > new file mode 100644
>
> > index 0000000..d0037bc
>
> > --- /dev/null
>
> > +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>
> > @@ -0,0 +1,52 @@
>
> > +%YAML 1.2
>
> > +---
>
> > +$id: "https://urldefense.proofpoint.com/v2/url?u=http-
> 3A__devicetree.org_schemas_phy_phy-2Dcadence-2Dtorrent.yaml-
> 23&d=DwICaQ&c=aUq983L2pue2FqKFoP6PGHMJQyoJ7kl3s3GZ-
> _haXqY&r=xythEVTj32hrXbonw_U5uD9n5Dh9J7TTTznvmGAGKo4&m=7Lsfbs
> we4WSrLOHdYWsEMjNHzy23kPJ6KPTggg6-8SU&s=jpJD4BVWnlZdjfrIyUu9E-
> NqOgIaq_idztPyQMeJlU0&e= "
>
> > +$schema: "https://urldefense.proofpoint.com/v2/url?u=http-
> 3A__devicetree.org_meta-2Dschemas_core.yaml-
> 23&d=DwICaQ&c=aUq983L2pue2FqKFoP6PGHMJQyoJ7kl3s3GZ-
> _haXqY&r=xythEVTj32hrXbonw_U5uD9n5Dh9J7TTTznvmGAGKo4&m=7Lsfbs
> we4WSrLOHdYWsEMjNHzy23kPJ6KPTggg6-
> 8SU&s=Jxp_SX84Yw0AHUVR90mknBvO23OsGXyqRMdcrJ3bpWc&e= "
>
> > +
>
> > +title: Cadence Torrent SD0801 PHY binding for DisplayPort
>
> > +
>
> > +description:
>
> > + This binding describes the Cadence SD0801 PHY hardware included with
>
> > + the Cadence MHDP DisplayPort controller.
>
> > +
>
> > +maintainers:
>
> > + - Kishon Vijay Abraham I <kishon@xxxxxx>
>
>
>
> No, This shouldn't be me.
Ok. Will change this.
>
> > +
>
> > +properties:
>
> > + compatible:
>
> > + const: cdns,torrent-phy
>
> > +
>
> > + reg:
>
> > + items:
>
> > + - description: Offset of the DPTX PHY configuration registers.
>
> > + - description: Offset of the SD0801 PHY configuration registers.
>
> > +
>
> > + "#phy-cells":
>
> > + const: 0
>
> > +
>
> > + num_lanes:
>
> > + maxItems: 1
>
> > + description:
>
> > + Number of DisplayPort lanes to use (1, 2 or 4)
>
>
>
> If this is a dt property, why is it also part of struct
>
> phy_configure_opts_dp?
Number of lanes field used in struct phy_configure_opts_dp is used during reconfiguration of link during link training, while dt property indicates initial max number of lanes supported. Number of lanes during reconfiguration can be less than or equal to max number of lanes.
>
> > +
>
> > + max_bit_rate:
>
> > + maxItems: 1
>
> > + description:
>
> > + Maximum DisplayPort link bit rate to use, in Mbps (2160, 2430, 2700,
> 3240, 4320, 5400 or 8100)
>
>
>
> Can't "enum" be used here to define the allowed bit rates?
Ok.
>
>
>
> Thanks
>
> Kishon
Thanks & Regards
Yuti Amonkar
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