Hi, Yongqiang: On Tue, 2019-11-26 at 14:47 +0800, yongqiang.niu@xxxxxxxxxxxx wrote: > From: Yongqiang Niu <yongqiang.niu@xxxxxxxxxxxx> > > This patch fix up 1440x900 dp display black screen issue > the computed result will overflow rdma1 fifo max size > when external display pixel clock bigger than 74MHZ > > Signed-off-by: Yongqiang Niu <yongqiang.niu@xxxxxxxxxxxx> > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index c1abde3..41143f5 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -152,6 +152,10 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > * account for blanking, and with a pixel depth of 4 bytes: > */ > threshold = width * height * vrefresh * 4 * 7 / 1000000; > + > + if (threshold > rdma_fifo_size) > + threshold = rdma_fifo_size; > + This looks like that threshold is over spec. I think this FIFO is used to cover the latency of reading data from DRAM. When data is read from OVL not RDMA, OVL already has a FIFO, so RDMA FIFO is useless. So I think you should set threshold to a special value when RDMA is in direct link mode. Regards, CK > reg = RDMA_FIFO_UNDERFLOW_EN | > RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
