On Tue, Nov 12, 2019 at 05:45:15PM +0100, Michel Dänzer wrote: > On 2019-11-11 8:29 p.m., Bjorn Helgaas wrote: > > From: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> > > > > Add definitions for these PCIe Link Control 2 register fields: > > > > Enter Compliance > > Transmit Margin > > > > and use them in amdgpu and radeon. > > > > NOTE: This is a functional change because "7 << 9" was apparently a typo. > > That mask included the high order bit of Transmit Margin, the Enter > > Modified Compliance bit, and the Compliance SOS bit, but I think what > > was intended was the 3-bit Transmit Margin field at bits 9:7. > > Can you split out the functional change into a separate patch 1? That > could make things easier for anyone who bisects the functional change > for whatever reason. Great idea, thanks! Wish I'd thought of that. While fixing that, I also noticed I missed one case in amdgpu/si.c. I'll post a v3. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
