On Tue, Nov 12, 2019 at 03:18:21PM +0100, Bas Vermeulen wrote:
> Hello,
>
> I am trying to create a new display mode for a new display I have to
> support.
>
> I have the following information:
>
> Dotclock - frequency period - 1/TCLP - 89.6 MHz
> TCDP - 11,16 ns
>
> Hsync - Period - TH - 2048 dotclock, 43,75 KHz, 22,86 us
> Pulse Width - THp - 40 dotclock, 0,45 us - active low, sync
> pulse high, polarity+
>
> Vsync - Period - TV - 729 dotclock, 60 Hz, 16,66 ms
> Pulse Width - TVp - 2 line, 45,72 us - active low, sync pulse
> high, polarity+
>
> Enable - Pulse Width - THd - 1920 dotclock
>
> V Display - Term - TVd - 720 line
> Start - TFd - 5 line
>
> Phase - Hsync-Enable - THe - 88 dotclock
> Hsync-Vsync - TVh - 0 dotclock
You don't happen to have an actual timing diagram to go along with
those?
>
> I made the following drm_display_mode out of it:
>
> { DRM_MODE("1920x720", DRM_MODE_TYPE_DRIVER, 89600, 1920, 1920,
> 1960, 2048, 0, 720, 722, 724, 729, 0,
The zero length horizontal front porch is perhaps a bit odd,
but looks like it could be correct given THp==40 and THe==88.
Also not sure about the the vertical front vs. back porch.
Maybe try swapping those around?
> DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
Not sure those are correct. It does says "active low" but then it has
that "sync pulse high, polarity+" stuff as well. Confusing. Could
be worth a shot to try flipping these.
--
Ville Syrjälä
Intel
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