The content of the base-address and offset registers are state of the primary plane. Clearing it to default values will interfere with plane functions for atomic mode setting. Signed-off-by: Thomas Zimmermann <tzimmermann@xxxxxxx> Acked-by: Gerd Hoffmann <kraxel@xxxxxxxxxx> --- drivers/gpu/drm/ast/ast_mode.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c index b13eaa2619ab..b3f82c2d274d 100644 --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@ -253,9 +253,13 @@ static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg); } - /* Set CRTC */ + /* Set CRTC; except base address and offset */ ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); - for (i = 0; i < 25; i++) + for (i = 0; i < 12; i++) + ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); + for (i = 14; i < 19; i++) + ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); + for (i = 20; i < 25; i++) ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); /* set AR */ -- 2.23.0 _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
