On Fri, Oct 25, 2019 at 11:57:38AM +0530, Bhanusree wrote:
> -Issue found using checkpatch.pl
> -Insert comments for memory barrier usage
>
> Signed-off-by: Bhanusree <bhanusreemahesh@xxxxxxxxx>
Thanks for your patch, applied.
-Daniel
> ---
> drivers/gpu/drm/drm_cache.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index 12f8d1b..03e01b0 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -126,10 +126,10 @@ drm_clflush_sg(struct sg_table *st)
> if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
> struct sg_page_iter sg_iter;
>
> - mb();
> + mb(); /*CLFLUSH is ordered only by using memory barriers*/
> for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
> drm_clflush_page(sg_page_iter_page(&sg_iter));
> - mb();
> + mb(); /*Make sure that all cache line entry is flushed*/
>
> return;
> }
> @@ -160,11 +160,11 @@ drm_clflush_virt_range(void *addr, unsigned long length)
> void *end = addr + length;
>
> addr = (void *)(((unsigned long)addr) & -size);
> - mb();
> + mb(); /*CLFLUSH is only ordered with a full memory barrier*/
> for (; addr < end; addr += size)
> clflushopt(addr);
> clflushopt(end - 1); /* force serialisation */
> - mb();
> + mb(); /*Ensure that evry data cache line entry is flushed*/
> return;
> }
>
> --
> 2.7.4
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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