On Tue, 17 Sep 2019 at 01:18, Thierry Reding <thierry.reding@xxxxxxxxx> wrote: > > From: Thierry Reding <treding@xxxxxxxxxx> > > The engine field in the FIFO fault information registers is actually 9 > bits wide. Looks like this is true for fault buffer parsing too. > > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx> > --- > drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c > index b5e32295237b..28306c5f6651 100644 > --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c > +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c > @@ -137,8 +137,8 @@ gv100_fault_intr_fault(struct nvkm_fault *fault) > info.addr = ((u64)addrhi << 32) | addrlo; > info.inst = ((u64)insthi << 32) | (info0 & 0xfffff000); > info.time = 0; > - info.engine = (info0 & 0x000000ff); > info.aperture = (info0 & 0x00000c00) >> 10; > + info.engine = (info0 & 0x000001ff); > info.valid = (info1 & 0x80000000) >> 31; > info.gpc = (info1 & 0x1f000000) >> 24; > info.hub = (info1 & 0x00100000) >> 20; > -- > 2.23.0 > > _______________________________________________ > Nouveau mailing list > Nouveau@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/nouveau _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
