Re: [PATCH v9 6/6] drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+

["Sharma, Shashank" <shashank.sharma@xxxxxxxxx>]

Regards

Shashank

On 8/22/2019 8:49 PM, Ramalingam C wrote:
>  From Gen12 onwards, HDCP HW block is implemented within transcoders.
> Till Gen11 HDCP HW block was part of DDI.
>
> Hence required changes in HW programming is handled here.
>
> As ME FW needs the transcoder detail on which HDCP is enabled
> on Gen12+ platform, we are populating the detail in hdcp_port_data.
>
> v2:
>    _MMIO_TRANS is used [Lucas and Daniel]
>    platform check is moved into the caller [Lucas]
> v3:
>    platform check is moved into a macro [Shashank]
> v4:
>    Few optimizations in the coding [Shashank]
> v5:
>    Fixed alignment in macro definition in i915_reg.h [Shashank]
>    unused variables "reg" is removed.
> v6:
>    Configuring the transcoder at compute_config.
>    transcoder is used instead of pipe in macros.
>    Rebased.
> v7:
>    transcoder is cached at intel_hdcp
>    hdcp_port_data is configured with transcoder index asper ME FW.
> v8:
>    s/trans/cpu_transcoder
>    s/tc/cpu_transcoder
>
> Signed-off-by: Ramalingam C <ramalingam.c@xxxxxxxxx>
> Reviewed-by: Shashank Sharma <shashank.sharma@xxxxxxxxx> [v5]
> Acked-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
>   drivers/gpu/drm/i915/display/intel_hdcp.c | 148 ++++++++++++++--------
>   drivers/gpu/drm/i915/display/intel_hdmi.c |  10 +-
>   drivers/gpu/drm/i915/i915_reg.h           | 124 ++++++++++++++++--
>   3 files changed, 219 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 1e5548833e8f..e2084403db27 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -18,6 +18,7 @@
>   #include "intel_display_types.h"
>   #include "intel_hdcp.h"
>   #include "intel_sideband.h"
> +#include "intel_connector.h"
>   
>   #define KEY_LOAD_TRIES	5
>   #define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS	50
> @@ -105,24 +106,20 @@ bool intel_hdcp2_capable(struct intel_connector *connector)
>   	return capable;
>   }
>   
> -static inline bool intel_hdcp_in_use(struct intel_connector *connector)
> +static inline
> +bool intel_hdcp_in_use(struct drm_i915_private *dev_priv,
> +		       enum transcoder cpu_transcoder, enum port port)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> -	enum port port = connector->encoder->port;
> -	u32 reg;
> -
> -	reg = I915_READ(PORT_HDCP_STATUS(port));
> -	return reg & HDCP_STATUS_ENC;
> +	return I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
> +	       HDCP_STATUS_ENC;
>   }
>   
> -static inline bool intel_hdcp2_in_use(struct intel_connector *connector)
> +static inline
> +bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv,
> +			enum transcoder cpu_transcoder, enum port port)
>   {
> -	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> -	enum port port = connector->encoder->port;
> -	u32 reg;
> -
> -	reg = I915_READ(HDCP2_STATUS_DDI(port));
> -	return reg & LINK_ENCRYPTION_STATUS;
> +	return I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
> +	       LINK_ENCRYPTION_STATUS;
>   }
>   
>   static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
> @@ -253,9 +250,28 @@ static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
>   }
>   
>   static
> -u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
> +u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv,
> +				enum transcoder cpu_transcoder, enum port port)
>   {
> -	enum port port = intel_dig_port->base.port;
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		switch (cpu_transcoder) {
> +		case TRANSCODER_A:
> +			return HDCP_TRANSA_REP_PRESENT |
> +			       HDCP_TRANSA_SHA1_M0;
> +		case TRANSCODER_B:
> +			return HDCP_TRANSB_REP_PRESENT |
> +			       HDCP_TRANSB_SHA1_M0;
> +		case TRANSCODER_C:
> +			return HDCP_TRANSC_REP_PRESENT |
> +			       HDCP_TRANSC_SHA1_M0;
> +		/* FIXME: Add a case for PIPE_D */
> +		default:
> +			DRM_ERROR("Unknown transcoder %d\n", cpu_transcoder);
> +			break;
> +		}
> +		return -EINVAL;
It doesn't make sense to have this return statement along sitting here, 
it should be up in with the default case; in place of break.
> +	}
> +
>   	switch (port) {
>   	case PORT_A:
>   		return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
> @@ -268,18 +284,21 @@ u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
>   	case PORT_E:
>   		return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
>   	default:
> +		DRM_ERROR("Unknown port %d\n", port);
>   		break;
>   	}
> -	DRM_ERROR("Unknown port %d\n", port);
>   	return -EINVAL;
>   }
>   
>   static
> -int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
> +int intel_hdcp_validate_v_prime(struct intel_connector *connector,
>   				const struct intel_hdcp_shim *shim,
>   				u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
>   {
> +	struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
>   	struct drm_i915_private *dev_priv;
> +	enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
> +	enum port port = intel_dig_port->base.port;
>   	u32 vprime, sha_text, sha_leftovers, rep_ctl;
>   	int ret, i, j, sha_idx;
>   
> @@ -306,7 +325,7 @@ int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
>   	sha_idx = 0;
>   	sha_text = 0;
>   	sha_leftovers = 0;
> -	rep_ctl = intel_hdcp_get_repeater_ctl(intel_dig_port);
> +	rep_ctl = intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder, port);
>   	I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
>   	for (i = 0; i < num_downstream; i++) {
>   		unsigned int sha_empty;
> @@ -548,7 +567,7 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector)
>   	 * V prime atleast twice.
>   	 */
>   	for (i = 0; i < tries; i++) {
> -		ret = intel_hdcp_validate_v_prime(intel_dig_port, shim,
> +		ret = intel_hdcp_validate_v_prime(connector, shim,
>   						  ksv_fifo, num_downstream,
>   						  bstatus);
>   		if (!ret)
> @@ -576,6 +595,7 @@ static int intel_hdcp_auth(struct intel_connector *connector)
>   	struct drm_device *dev = connector->base.dev;
>   	const struct intel_hdcp_shim *shim = hdcp->shim;
>   	struct drm_i915_private *dev_priv;
> +	enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
>   	enum port port;
>   	unsigned long r0_prime_gen_start;
>   	int ret, i, tries = 2;
> @@ -615,18 +635,21 @@ static int intel_hdcp_auth(struct intel_connector *connector)
>   
>   	/* Initialize An with 2 random values and acquire it */
>   	for (i = 0; i < 2; i++)
> -		I915_WRITE(PORT_HDCP_ANINIT(port), get_random_u32());
> -	I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN);
> +		I915_WRITE(HDCP_ANINIT(dev_priv, cpu_transcoder, port),
> +			   get_random_u32());
> +	I915_WRITE(HDCP_CONF(dev_priv, cpu_transcoder, port),
> +		   HDCP_CONF_CAPTURE_AN);
>   
>   	/* Wait for An to be acquired */
> -	if (intel_de_wait_for_set(dev_priv, PORT_HDCP_STATUS(port),
> +	if (intel_de_wait_for_set(dev_priv,
> +				  HDCP_STATUS(dev_priv, cpu_transcoder, port),
>   				  HDCP_STATUS_AN_READY, 1)) {
>   		DRM_ERROR("Timed out waiting for An\n");
>   		return -ETIMEDOUT;
>   	}
>   
> -	an.reg[0] = I915_READ(PORT_HDCP_ANLO(port));
> -	an.reg[1] = I915_READ(PORT_HDCP_ANHI(port));
> +	an.reg[0] = I915_READ(HDCP_ANLO(dev_priv, cpu_transcoder, port));
> +	an.reg[1] = I915_READ(HDCP_ANHI(dev_priv, cpu_transcoder, port));
>   	ret = shim->write_an_aksv(intel_dig_port, an.shim);
>   	if (ret)
>   		return ret;
> @@ -644,24 +667,26 @@ static int intel_hdcp_auth(struct intel_connector *connector)
>   		return -EPERM;
>   	}
>   
> -	I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
> -	I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
> +	I915_WRITE(HDCP_BKSVLO(dev_priv, cpu_transcoder, port), bksv.reg[0]);
> +	I915_WRITE(HDCP_BKSVHI(dev_priv, cpu_transcoder, port), bksv.reg[1]);
>   
>   	ret = shim->repeater_present(intel_dig_port, &repeater_present);
>   	if (ret)
>   		return ret;
>   	if (repeater_present)
>   		I915_WRITE(HDCP_REP_CTL,
> -			   intel_hdcp_get_repeater_ctl(intel_dig_port));
> +			   intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder,
> +						       port));
>   
>   	ret = shim->toggle_signalling(intel_dig_port, true);
>   	if (ret)
>   		return ret;
>   
> -	I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_AUTH_AND_ENC);
> +	I915_WRITE(HDCP_CONF(dev_priv, cpu_transcoder, port),
> +		   HDCP_CONF_AUTH_AND_ENC);
>   
>   	/* Wait for R0 ready */
> -	if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> +	if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
>   		     (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) {
>   		DRM_ERROR("Timed out waiting for R0 ready\n");
>   		return -ETIMEDOUT;
> @@ -689,22 +714,25 @@ static int intel_hdcp_auth(struct intel_connector *connector)
>   		ret = shim->read_ri_prime(intel_dig_port, ri.shim);
>   		if (ret)
>   			return ret;
> -		I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
> +		I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg);
>   
>   		/* Wait for Ri prime match */
> -		if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> +		if (!wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
> +						    port)) &
>   		    (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
>   			break;
>   	}
>   
>   	if (i == tries) {
>   		DRM_DEBUG_KMS("Timed out waiting for Ri prime match (%x)\n",
> -			      I915_READ(PORT_HDCP_STATUS(port)));
> +			      I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
> +						    port)));
>   		return -ETIMEDOUT;
>   	}
>   
>   	/* Wait for encryption confirmation */
> -	if (intel_de_wait_for_set(dev_priv, PORT_HDCP_STATUS(port),
> +	if (intel_de_wait_for_set(dev_priv,
> +				  HDCP_STATUS(dev_priv, cpu_transcoder, port),
>   				  HDCP_STATUS_ENC,
>   				  ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
>   		DRM_ERROR("Timed out waiting for encryption\n");
> @@ -729,15 +757,17 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
>   	struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
>   	struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
>   	enum port port = intel_dig_port->base.port;
> +	enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
>   	int ret;
>   
>   	DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n",
>   		      connector->base.name, connector->base.base.id);
>   
>   	hdcp->hdcp_encrypted = false;
> -	I915_WRITE(PORT_HDCP_CONF(port), 0);
> -	if (intel_de_wait_for_clear(dev_priv, PORT_HDCP_STATUS(port), ~0,
> -				    ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> +	I915_WRITE(HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
> +	if (intel_de_wait_for_clear(dev_priv,
> +				    HDCP_STATUS(dev_priv, cpu_transcoder, port),
> +				    ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
>   		DRM_ERROR("Failed to disable HDCP, timeout clearing status\n");
>   		return -ETIMEDOUT;
>   	}
> @@ -808,9 +838,11 @@ static int intel_hdcp_check_link(struct intel_connector *connector)
>   	struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
>   	struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
>   	enum port port = intel_dig_port->base.port;
> +	enum transcoder cpu_transcoder;
>   	int ret = 0;
>   
>   	mutex_lock(&hdcp->mutex);
> +	cpu_transcoder = hdcp->cpu_transcoder;
>   
>   	/* Check_link valid only when HDCP1.4 is enabled */
>   	if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
> @@ -819,10 +851,11 @@ static int intel_hdcp_check_link(struct intel_connector *connector)
>   		goto out;
>   	}
>   
> -	if (WARN_ON(!intel_hdcp_in_use(connector))) {
> +	if (WARN_ON(!intel_hdcp_in_use(dev_priv, cpu_transcoder, port))) {
>   		DRM_ERROR("%s:%d HDCP link stopped encryption,%x\n",
>   			  connector->base.name, connector->base.base.id,
> -			  I915_READ(PORT_HDCP_STATUS(port)));
> +			  I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
> +						port)));
>   		ret = -ENXIO;
>   		hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
>   		schedule_work(&hdcp->prop_work);
> @@ -1493,10 +1526,11 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
>   	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>   	struct intel_hdcp *hdcp = &connector->hdcp;
>   	enum port port = connector->encoder->port;
> +	enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
>   	int ret;
>   
> -	WARN_ON(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS);
> -
> +	WARN_ON(I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
> +		LINK_ENCRYPTION_STATUS);
>   	if (hdcp->shim->toggle_signalling) {
>   		ret = hdcp->shim->toggle_signalling(intel_dig_port, true);
>   		if (ret) {
> @@ -1506,14 +1540,18 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
>   		}
>   	}
>   
> -	if (I915_READ(HDCP2_STATUS_DDI(port)) & LINK_AUTH_STATUS) {
> +	if (I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
> +	    LINK_AUTH_STATUS) {
>   		/* Link is Authenticated. Now set for Encryption */
> -		I915_WRITE(HDCP2_CTL_DDI(port),
> -			   I915_READ(HDCP2_CTL_DDI(port)) |
> +		I915_WRITE(HDCP2_CTL(dev_priv, cpu_transcoder, port),
> +			   I915_READ(HDCP2_CTL(dev_priv, cpu_transcoder,
> +					       port)) |
>   			   CTL_LINK_ENCRYPTION_REQ);
>   	}
>   
> -	ret = intel_de_wait_for_set(dev_priv, HDCP2_STATUS_DDI(port),
> +	ret = intel_de_wait_for_set(dev_priv,
> +				    HDCP2_STATUS(dev_priv, cpu_transcoder,
> +						 port),
>   				    LINK_ENCRYPTION_STATUS,
>   				    ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
>   
> @@ -1526,14 +1564,19 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
>   	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>   	struct intel_hdcp *hdcp = &connector->hdcp;
>   	enum port port = connector->encoder->port;
> +	enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
>   	int ret;
>   
> -	WARN_ON(!(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS));
> +	WARN_ON(!(I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
> +			    LINK_ENCRYPTION_STATUS));
>   
> -	I915_WRITE(HDCP2_CTL_DDI(port),
> -		   I915_READ(HDCP2_CTL_DDI(port)) & ~CTL_LINK_ENCRYPTION_REQ);
> +	I915_WRITE(HDCP2_CTL(dev_priv, cpu_transcoder, port),
> +		   I915_READ(HDCP2_CTL(dev_priv, cpu_transcoder, port)) &
> +		   ~CTL_LINK_ENCRYPTION_REQ);
>   
> -	ret = intel_de_wait_for_clear(dev_priv, HDCP2_STATUS_DDI(port),
> +	ret = intel_de_wait_for_clear(dev_priv,
> +				      HDCP2_STATUS(dev_priv, cpu_transcoder,
> +						   port),
>   				      LINK_ENCRYPTION_STATUS,
>   				      ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
>   	if (ret == -ETIMEDOUT)
> @@ -1632,9 +1675,11 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
>   	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>   	struct intel_hdcp *hdcp = &connector->hdcp;
>   	enum port port = connector->encoder->port;
> +	enum transcoder cpu_transcoder;
>   	int ret = 0;
>   
>   	mutex_lock(&hdcp->mutex);
> +	cpu_transcoder = hdcp->cpu_transcoder;
>   
>   	/* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
>   	if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED ||
> @@ -1643,9 +1688,10 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
>   		goto out;
>   	}
>   
> -	if (WARN_ON(!intel_hdcp2_in_use(connector))) {
> +	if (WARN_ON(!intel_hdcp2_in_use(dev_priv, cpu_transcoder, port))) {
>   		DRM_ERROR("HDCP2.2 link stopped the encryption, %x\n",
> -			  I915_READ(HDCP2_STATUS_DDI(port)));
> +			  I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder,
> +						 port)));
>   		ret = -ENXIO;
>   		hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
>   		schedule_work(&hdcp->prop_work);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 6e9bb6bd1ee2..f6bb77fd0930 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1491,7 +1491,10 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
>   {
>   	struct drm_i915_private *dev_priv =
>   		intel_dig_port->base.base.dev->dev_private;
> +	struct intel_connector *connector =
> +		intel_dig_port->hdmi.attached_connector;
>   	enum port port = intel_dig_port->base.port;
> +	enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
>   	int ret;
>   	union {
>   		u32 reg;
> @@ -1502,13 +1505,14 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
>   	if (ret)
>   		return false;
>   
> -	I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
> +	I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg);
>   
>   	/* Wait for Ri prime match */
> -	if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> +	if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
>   		     (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
>   		DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
> -			  I915_READ(PORT_HDCP_STATUS(port)));
> +			  I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
> +						port)));
>   		return false;
>   	}
>   	return true;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2abd199093c5..572e4cba847a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9256,12 +9256,20 @@ enum skl_power_gate {
>   
>   /* HDCP Repeater Registers */
>   #define HDCP_REP_CTL			_MMIO(0x66d00)
> +#define  HDCP_TRANSA_REP_PRESENT	BIT(31)
> +#define  HDCP_TRANSB_REP_PRESENT	BIT(30)
> +#define  HDCP_TRANSC_REP_PRESENT	BIT(29)
> +#define  HDCP_TRANSD_REP_PRESENT	BIT(28)
>   #define  HDCP_DDIB_REP_PRESENT		BIT(30)
>   #define  HDCP_DDIA_REP_PRESENT		BIT(29)
>   #define  HDCP_DDIC_REP_PRESENT		BIT(28)
>   #define  HDCP_DDID_REP_PRESENT		BIT(27)
>   #define  HDCP_DDIF_REP_PRESENT		BIT(26)
>   #define  HDCP_DDIE_REP_PRESENT		BIT(25)
> +#define  HDCP_TRANSA_SHA1_M0		(1 << 20)
> +#define  HDCP_TRANSB_SHA1_M0		(2 << 20)
> +#define  HDCP_TRANSC_SHA1_M0		(3 << 20)
> +#define  HDCP_TRANSD_SHA1_M0		(4 << 20)
>   #define  HDCP_DDIB_SHA1_M0		(1 << 20)
>   #define  HDCP_DDIA_SHA1_M0		(2 << 20)
>   #define  HDCP_DDIC_SHA1_M0		(3 << 20)
> @@ -9301,15 +9309,92 @@ enum skl_power_gate {
>   					  _PORTE_HDCP_AUTHENC, \
>   					  _PORTF_HDCP_AUTHENC) + (x))
>   #define PORT_HDCP_CONF(port)		_PORT_HDCP_AUTHENC(port, 0x0)
> +#define _TRANSA_HDCP_CONF		0x66400
> +#define _TRANSB_HDCP_CONF		0x66500
> +#define TRANS_HDCP_CONF(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
> +						    _TRANSB_HDCP_CONF)
> +#define HDCP_CONF(dev_priv, trans, port) \
> +					(INTEL_GEN(dev_priv) >= 12 ? \
> +					 TRANS_HDCP_CONF(trans) : \
> +					 PORT_HDCP_CONF(port))
> +
>   #define  HDCP_CONF_CAPTURE_AN		BIT(0)
>   #define  HDCP_CONF_AUTH_AND_ENC		(BIT(1) | BIT(0))
>   #define PORT_HDCP_ANINIT(port)		_PORT_HDCP_AUTHENC(port, 0x4)
> +#define _TRANSA_HDCP_ANINIT		0x66404
> +#define _TRANSB_HDCP_ANINIT		0x66504
> +#define TRANS_HDCP_ANINIT(trans)	_MMIO_TRANS(trans, \
> +						    _TRANSA_HDCP_ANINIT, \
> +						    _TRANSB_HDCP_ANINIT)
> +#define HDCP_ANINIT(dev_priv, trans, port) \
> +					(INTEL_GEN(dev_priv) >= 12 ? \
> +					 TRANS_HDCP_ANINIT(trans) : \
> +					 PORT_HDCP_ANINIT(port))
> +
>   #define PORT_HDCP_ANLO(port)		_PORT_HDCP_AUTHENC(port, 0x8)
> +#define _TRANSA_HDCP_ANLO		0x66408
> +#define _TRANSB_HDCP_ANLO		0x66508
> +#define TRANS_HDCP_ANLO(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
> +						    _TRANSB_HDCP_ANLO)
> +#define HDCP_ANLO(dev_priv, trans, port) \
> +					(INTEL_GEN(dev_priv) >= 12 ? \
> +					 TRANS_HDCP_ANLO(trans) : \
> +					 PORT_HDCP_ANLO(port))
> +
>   #define PORT_HDCP_ANHI(port)		_PORT_HDCP_AUTHENC(port, 0xC)
> +#define _TRANSA_HDCP_ANHI		0x6640C
> +#define _TRANSB_HDCP_ANHI		0x6650C
> +#define TRANS_HDCP_ANHI(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
> +						    _TRANSB_HDCP_ANHI)
> +#define HDCP_ANHI(dev_priv, trans, port) \
> +					(INTEL_GEN(dev_priv) >= 12 ? \
> +					 TRANS_HDCP_ANHI(trans) : \
> +					 PORT_HDCP_ANHI(port))
> +
>   #define PORT_HDCP_BKSVLO(port)		_PORT_HDCP_AUTHENC(port, 0x10)
> +#define _TRANSA_HDCP_BKSVLO		0x66410
> +#define _TRANSB_HDCP_BKSVLO		0x66510
> +#define TRANS_HDCP_BKSVLO(trans)	_MMIO_TRANS(trans, \
> +						    _TRANSA_HDCP_BKSVLO, \
> +						    _TRANSB_HDCP_BKSVLO)
> +#define HDCP_BKSVLO(dev_priv, trans, port) \
> +					(INTEL_GEN(dev_priv) >= 12 ? \
> +					 TRANS_HDCP_BKSVLO(trans) : \
> +					 PORT_HDCP_BKSVLO(port))
> +
>   #define PORT_HDCP_BKSVHI(port)		_PORT_HDCP_AUTHENC(port, 0x14)
> +#define _TRANSA_HDCP_BKSVHI		0x66414
> +#define _TRANSB_HDCP_BKSVHI		0x66514
> +#define TRANS_HDCP_BKSVHI(trans)	_MMIO_TRANS(trans, \
> +						    _TRANSA_HDCP_BKSVHI, \
> +						    _TRANSB_HDCP_BKSVHI)
> +#define HDCP_BKSVHI(dev_priv, trans, port) \
> +					(INTEL_GEN(dev_priv) >= 12 ? \
> +					 TRANS_HDCP_BKSVHI(trans) : \
> +					 PORT_HDCP_BKSVHI(port))
> +
>   #define PORT_HDCP_RPRIME(port)		_PORT_HDCP_AUTHENC(port, 0x18)
> +#define _TRANSA_HDCP_RPRIME		0x66418
> +#define _TRANSB_HDCP_RPRIME		0x66518
> +#define TRANS_HDCP_RPRIME(trans)	_MMIO_TRANS(trans, \
> +						    _TRANSA_HDCP_RPRIME, \
> +						    _TRANSB_HDCP_RPRIME)
> +#define HDCP_RPRIME(dev_priv, trans, port) \
> +					(INTEL_GEN(dev_priv) >= 12 ? \
> +					 TRANS_HDCP_RPRIME(trans) : \
> +					 PORT_HDCP_RPRIME(port))
> +
>   #define PORT_HDCP_STATUS(port)		_PORT_HDCP_AUTHENC(port, 0x1C)
> +#define _TRANSA_HDCP_STATUS		0x6641C
> +#define _TRANSB_HDCP_STATUS		0x6651C
> +#define TRANS_HDCP_STATUS(trans)	_MMIO_TRANS(trans, \
> +						    _TRANSA_HDCP_STATUS, \
> +						    _TRANSB_HDCP_STATUS)
> +#define HDCP_STATUS(dev_priv, trans, port) \
> +					(INTEL_GEN(dev_priv) >= 12 ? \
> +					 TRANS_HDCP_STATUS(trans) : \
> +					 PORT_HDCP_STATUS(port))
> +
>   #define  HDCP_STATUS_STREAM_A_ENC	BIT(31)
>   #define  HDCP_STATUS_STREAM_B_ENC	BIT(30)
>   #define  HDCP_STATUS_STREAM_C_ENC	BIT(29)
> @@ -9336,23 +9421,44 @@ enum skl_power_gate {
>   					  _PORTD_HDCP2_BASE, \
>   					  _PORTE_HDCP2_BASE, \
>   					  _PORTF_HDCP2_BASE) + (x))
> -
> -#define HDCP2_AUTH_DDI(port)		_PORT_HDCP2_BASE(port, 0x98)
> +#define PORT_HDCP2_AUTH(port)		_PORT_HDCP2_BASE(port, 0x98)
> +#define _TRANSA_HDCP2_AUTH		0x66498
> +#define _TRANSB_HDCP2_AUTH		0x66598
> +#define TRANS_HDCP2_AUTH(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \
> +						    _TRANSB_HDCP2_AUTH)
>   #define   AUTH_LINK_AUTHENTICATED	BIT(31)
>   #define   AUTH_LINK_TYPE		BIT(30)
>   #define   AUTH_FORCE_CLR_INPUTCTR	BIT(19)
>   #define   AUTH_CLR_KEYS			BIT(18)
> -
> -#define HDCP2_CTL_DDI(port)		_PORT_HDCP2_BASE(port, 0xB0)
> +#define HDCP2_AUTH(dev_priv, trans, port) \
> +					(INTEL_GEN(dev_priv) >= 12 ? \
> +					 TRANS_HDCP2_AUTH(trans) : \
> +					 PORT_HDCP2_AUTH(port))
> +
> +#define PORT_HDCP2_CTL(port)		_PORT_HDCP2_BASE(port, 0xB0)
> +#define _TRANSA_HDCP2_CTL		0x664B0
> +#define _TRANSB_HDCP2_CTL		0x665B0
> +#define TRANS_HDCP2_CTL(trans)		_MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \
> +						    _TRANSB_HDCP2_CTL)
>   #define   CTL_LINK_ENCRYPTION_REQ	BIT(31)
> -
> -#define HDCP2_STATUS_DDI(port)		_PORT_HDCP2_BASE(port, 0xB4)
> -#define   STREAM_ENCRYPTION_STATUS_A	BIT(31)
> -#define   STREAM_ENCRYPTION_STATUS_B	BIT(30)
> -#define   STREAM_ENCRYPTION_STATUS_C	BIT(29)
> +#define HDCP2_CTL(dev_priv, trans, port) \
> +					(INTEL_GEN(dev_priv) >= 12 ? \
> +					 TRANS_HDCP2_CTL(trans) : \
> +					 PORT_HDCP2_CTL(port))
> +
> +#define PORT_HDCP2_STATUS(port)		_PORT_HDCP2_BASE(port, 0xB4)
> +#define _TRANSA_HDCP2_STATUS		0x664B4
> +#define _TRANSB_HDCP2_STATUS		0x665B4
> +#define TRANS_HDCP2_STATUS(trans)	_MMIO_TRANS(trans, \
> +						    _TRANSA_HDCP2_STATUS, \
> +						    _TRANSB_HDCP2_STATUS)
>   #define   LINK_TYPE_STATUS		BIT(22)
>   #define   LINK_AUTH_STATUS		BIT(21)
>   #define   LINK_ENCRYPTION_STATUS	BIT(20)
> +#define HDCP2_STATUS(dev_priv, trans, port) \
> +					(INTEL_GEN(dev_priv) >= 12 ? \
> +					 TRANS_HDCP2_STATUS(trans) : \
> +					 PORT_HDCP2_STATUS(port))
>   
>   /* Per-pipe DDI Function Control */
>   #define _TRANS_DDI_FUNC_CTL_A		0x60400

I cross checked the deltas between V5 to V9, they seem ok,

You can carry forward my R-B from V5.

- Shashank


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