Am Montag, 1. April 2019, 19:17:24 CEST schrieb Douglas Anderson: > Just like we did for rk3288-veyron-chromebook, we want to be able to > use one of the fixed PLLs in the system to make the pixel clock for > minnie. > > Specifying these timings matches us with how the display is used on > the downstream Chrome OS kernel. See https://crrev.com/c/323211. > > Unlike what we did for rk3288-veyron-chromebook, this CL actually > changes the timings (though not the pixel clock) that is used when > using the upstream kernel. Booting up a minnie shows that it ended up > with a 66.67 MHz pixel clock but it was still using the > porches/blankings it would have wanted for a 72.5 MHz pixel clock. > > NOTE: compared to the downstream kernel, this seems to cause a > slightly different result reported in the 'modetest' command on a > Chromebook. The downstream kernel shows: > 1280x800 60 1280 1298 1330 1351 800 804 822 830 66667 > > With this patch we have: > 1280x800 59 1280 1298 1330 1351 800 804 822 830 66666 > > Specifically modetest was reporting 60 Hz on the downstream kernel but > the upstream kernel does the math and comesup with 59 (because we > actually achieve 59.45 Hz). Also upstream doesn't round the Hz up > when converting to kHz--it seems to truncate. > > ALSO NOTE: when I look at the EDID from the datasheet, I see: > -hsync -vsync > ...but it seems like we've never actually run with that so I've > continued leaving that out. > > Signed-off-by: Douglas Anderson <dianders@xxxxxxxxxxxx> applied for 5.4 Thanks Heiko _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
