On Wed, Jan 23, 2019 at 9:24 PM Maxime Ripard <maxime.ripard@xxxxxxxxxxx> wrote: > > The current code allows the TCON clock divider to have a range between 4 > and 127 when feeding the DSI controller. > > The only display supported so far had a display clock rate that ended up > using a divider of 4, but testing with other displays show that only 4 > seems to be functional. > > This also aligns with what Allwinner is doing in their BSP, so let's just > hardcode that we want a divider of 4 when using the DSI output. So, bad that existing dotclock is unable to produce the desired divider logic. I have tried certain possibilities wrt changing the clock rate in pll-mipi via min_rate, but it eventually not working with all panels. Yes, I have seen Allwinner BSP has logic to this dividers wrt SoC's. for A33 it's default to 4 but for A64 it computed in other-way wrt format and lanes. Let me send the change wrt format and lanes, I'm hoping the same will work with existing display or If you have any inputs please let me know. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
