On Fri, Jan 25, 2019 at 01:28:49AM +0530, Jagan Teki wrote: > Minimum PLL used for MIPI is 500MHz, as per manual, but > lowering the min rate by 300MHz can result proper working > nkms divider with the help of desired dclock rate from > panel driver. > > Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> > Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx> Going 200MHz below the minimum doesn't seem really reasonable. What is the issue that you are trying to fix here? It looks like it's picking bad dividers, but if that's the case, this isn't the proper fix. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
