On Fri, Dec 14, 2018 at 1:25 AM Sean Paul <sean@xxxxxxxxxx> wrote: > > On Fri, Dec 14, 2018 at 12:56:03AM +0530, Jagan Teki wrote: > > On Thu, Dec 13, 2018 at 8:37 PM Sean Paul <sean@xxxxxxxxxx> wrote: > > > > > > On Fri, Nov 16, 2018 at 10:09:15PM +0530, Jagan Teki wrote: > > > > Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel. > > > > > > > > Add panel driver for it. > > > > > > > > Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> > > > > --- > > > > MAINTAINERS | 6 + > > > > drivers/gpu/drm/panel/Kconfig | 9 + > > > > drivers/gpu/drm/panel/Makefile | 1 + > > > > .../drm/panel/panel-feiyang-fy07024di26a30d.c | 286 ++++++++++++++++++ > > > > 4 files changed, 302 insertions(+) > > > > create mode 100644 drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c > > > > > > /snip > > > > > diff --git a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c > > > > new file mode 100644 > > > > index 000000000000..a4b46bd8fdbe > > > > --- /dev/null > > > > +++ b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c > > /snip > > > > > +static int feiyang_prepare(struct drm_panel *panel) > > > > +{ > > > > + struct feiyang *ctx = panel_to_feiyang(panel); > > > > + struct mipi_dsi_device *dsi = ctx->dsi; > > > > + unsigned int i; > > > > + int ret; > > > > + > > > > + ret = regulator_enable(ctx->dvdd); > > > > + if (ret) > > > > + return ret; > > > > + > > > > + msleep(100); > > > > > > nit: You should do your best to correlate the sleeps with the timing parameters > > > from the datasheet with a comment. > > > > > > ie: > > > /* T1: > 100ms */ > > > msleep(100); > > > > Sorry, what does this mean? > > On page 9 of the datasheet you sent me [1], it has the delays required to safely > power up the panel. This delay is the time between dvdd going high and avdd > going high. On the figure in the datasheet, this would be T2 (T1 is dvdd rise time between dvdd going high and avdd going high is T1 + T3 right? T2 > 0ms T3 > 20ms In this case the delay can be msleep(20) ? > time and should be handled in the regulator subsystem (iirc)). Also according to > the datasheet, T2 just needs to be > 0, so you don't even need this delay. You > could replace this with a comment like: > > /* T1 (dvdd rise time) + T2 (dvdd->avdd) > 0 */ > > So for all of the msleeps below you should get the delays from the datasheet and > add a comment referencing them. T5 and T6 are delay between avdd to reset enable it can be 10 + 10 => 20ms and finally T12 which is 200 after reset. What about the delay between resets, I need to understand it a bit. _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel