On Tue, Dec 04, 2018 at 03:22:09PM +0100, Paul Kocialkowski wrote:
> This introduces stride and offset configuration for the VPU tiling mode.
> Stride is calculated differently than it is for linear formats and an
> offset is calculated, for which new register definitions are introduced.
>
> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@xxxxxxxxxxx>
> ---
> drivers/gpu/drm/sun4i/sun4i_frontend.c | 60 ++++++++++++++++++++++++--
> drivers/gpu/drm/sun4i/sun4i_frontend.h | 8 ++++
> 2 files changed, 65 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_frontend.c b/drivers/gpu/drm/sun4i/sun4i_frontend.c
> index 3dcb05147e41..151b78d3c02e 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_frontend.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_frontend.c
> @@ -125,21 +125,75 @@ void sun4i_frontend_update_buffer(struct sun4i_frontend *frontend,
> {
> struct drm_plane_state *state = plane->state;
> struct drm_framebuffer *fb = state->fb;
> + unsigned int strides[3] = {};
> +
> dma_addr_t paddr;
> bool swap;
>
> + if (fb->modifier == DRM_FORMAT_MOD_ALLWINNER_TILED) {
> + unsigned int width = state->src_w >> 16;
> + unsigned int offset;
> +
> + /*
> + * In MB32 tiled mode, the stride is defined as the distance
> + * between the start of the end line of the current tile and
> + * the start of the first line in the next vertical tile.
> + *
> + * Tiles are represented in row-major order, thus the end line
> + * of current tile starts at: 31 * 32 (31 lines of 32 cols),
> + * the next vertical tile starts at: 32-bit-aligned-width * 32
> + * and the distance is: 32 * (32-bit-aligned-width - 31).
> + */
It'd be better if that comment was next to the macro definition where
the code is.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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