Hi folks,
I just randomly add some people that committed code to the
DSI core so I can get some reasonable feedback.
I started looking at some DSI drivers I'm adding and it seems
this platform (Ux500 MCDE) can control the bus frequency
of the DSI interface. It can be controlled independently for
command and video mode, and there is an LP (low power)
frequency and a HS (high speed) frequency for the lane.
The MIPI specification seems to say "The maximum Lane
frequency shall be documented by the DSI device manufacturer."
Then it goes on to specify tolerance for the HS and LP
frequency.
So apparently those are not standard frequencies.
I was thinking to add something like this:
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 4fef19064b0f..9c78eb78b027 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -168,6 +168,8 @@ struct mipi_dsi_device_info {
* @format: pixel format for video mode
* @lanes: number of active data lanes
* @mode_flags: DSI operation mode related flags
+ * @hs_frequency: Maximum frequency for high speed operation
+ * @lp_frequency: Maximum frequency for low power operation
*/
struct mipi_dsi_device {
struct mipi_dsi_host *host;
@@ -178,6 +180,8 @@ struct mipi_dsi_device {
unsigned int lanes;
enum mipi_dsi_pixel_format format;
unsigned long mode_flags;
+ unsigned long hs_frequency;
+ unsigned long lp_frequency;
};
Is this what we should do to make DSI panels expose their max
LS/HS frequency? (If zero, we could assume some default
I guess.)
Yours,
Linus Walleij
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