On Thu, Sep 27, 2018 at 05:18:44PM +0530, Jagan Teki wrote: > According to horizontal and vertical timings are defined > per the diagram from include/drm/drm_modes.h > > Back porch = [hv]total - [hv]sync_end > > So, update SUN6I_DSI_BASIC_SIZE0_VBP calculation as > mode->vtotal - mode->vsync_end > > Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > index 1c7e42015645..599284971ab6 100644 > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c > @@ -526,8 +526,8 @@ static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi, > regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE0_REG, > SUN6I_DSI_BASIC_SIZE0_VSA(mode->vsync_end - > mode->vsync_start) | > - SUN6I_DSI_BASIC_SIZE0_VBP(mode->vsync_start - > - mode->vdisplay)); > + SUN6I_DSI_BASIC_SIZE0_VBP(mode->vtotal - > + mode->vsync_end)); Is it purely theoretical, or did you find some source that back that? Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
