Hi Ulrich,
I know this series needs to be re-spin when the D3/E3 LVDS PLL
support will be added, but since I need it for testing on D3 the LVDS
interface reset support, I noticed a small issue which I thought it is
worth reporting.
On Tue, May 15, 2018 at 02:20:38PM +0200, Ulrich Hecht wrote:
> From: Kieran Bingham <kieran.bingham+renesas@xxxxxxxxxxxxxxxx>
>
> The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@xxxxxxxxxxxxxxxx>
> [uli: moved lvds* into the soc node, added PM domains, resets]
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@xxxxxxxxx>
> ---
> arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 +++++++++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> index ba98865..8e78110d 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> @@ -757,12 +757,68 @@
> port@1 {
> reg = <1>;
> du_out_lvds0: endpoint {
> + remote-endpoint = <&lvds0_in>;
> };
> };
>
> port@2 {
> reg = <2>;
> du_out_lvds1: endpoint {
> + remote-endpoint = <&lvds1_in>;
> + };
> + };
> + };
> + };
> +
> + lvds0: lvds-encoder@feb90000 {
> + compatible = "renesas,r8a77995-lvds";
> + reg = <0 0xfeb90000 0 0x20>;
> + clocks = <&cpg CPG_MOD 727>;
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 727>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + lvds0_in: endpoint {
> + remote-endpoint = <&du_out_lvds0>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + lvds0_out: endpoint {
> + };
> + };
> + };
> + };
> +
> + lvds1: lvds-encoder@feb90100 {
> + compatible = "renesas,r8a77995-lvds";
> + reg = <0 0xfeb90100 0 0x20>;
> + clocks = <&cpg CPG_MOD 727>;
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 727>;
The LVDS-IF1 CPG reset is SRCR7[26], this I think this should be
<&cpg 726>
Please note that the most recent chip manual release has probably an
error at page 3180, section 37-32
5. When display on in the LVDS0-IF, it is necessary to reset (SRCR7[27]) and reset clearing (SRSTCLR7[27])
LVDS0-IF module.
When display on in the LVDS1-IF, it is necessary to reset (SRCR7[26]) and reset clearing (SRSTCLR7[26])
LVDS0-IF module
^- This should probablt be LVDS1-IF
Thanks
j
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + lvds1_in: endpoint {
> + remote-endpoint = <&du_out_lvds1>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + lvds1_out: endpoint {
> };
> };
> };
> --
> 2.7.4
>
Attachment:
signature.asc
Description: PGP signature
_______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
