Quoting Rob Herring (2018-06-13 08:03:53) > On Wed, Jun 13, 2018 at 5:08 AM, Sandeep Panda <spanda@xxxxxxxxxxxxxx> wrote: > > +Optional properties: > > +- interrupts: Specifier for the SN65DSI86 interrupt line. > > + > > +- ddc-i2c-bus: phandle of the I2C controller used for DDC EDID probing > > + > > +- gpio-controller: Marks the device has a GPIO controller. > > +- #gpio-cells : Should be two. The first cell is the pin number and > > + the second cell is used to specify flags. > > + See ../../gpio/gpio.txt for more information. > > +- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description of > > + the cell formats. > > + > > +- clock-names: should be "refclk" > > +- clocks: Specification for input reference clock. The reference > > + clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz. > > + > > +- data-lanes: Specification to describe the logical to physical lane > > + mapping scheme. See ../../media/video-interface.txt for more > > + information. > > +- lane-polarities: Specification to describe the polarity of physical lanes. > > + See ../../media/video-interface.txt for more information. > > You are still defining the properties here. All you need is: > > data-lanes: See ../../media/video-interface.txt > > Perhaps you need to say should be 4 lanes, but OTOH everything tends > to be 4 lanes. > Maybe also indicate what logical to physical data lanes are being remapped by saying something to the effect of "logical to physical DSI lane mapping scheme". _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
