On Wed, Jun 13, 2018 at 5:08 AM, Sandeep Panda <spanda@xxxxxxxxxxxxxx> wrote: > Document the bindings used for the sn65dsi86 DSI to eDP bridge. > > Changes in v1: > - Rephrase the dt-binding descriptions to be more inline with existing > bindings (Andrzej Hajda). > - Add missing dt-binding that are parsed by corresponding driver > (Andrzej Hajda). > > Changes in v2: > - Remove edp panel specific dt-binding entries. Only keep bridge > specific entries (Sean Paul). > - Remove custom-modes dt entry since its usage is removed from driver also (Sean Paul). > - Remove is-pluggable dt entry since this will not be needed anymore (Sean Paul). > > Changes in v3: > - Remove irq-gpio dt entry and instead populate is an interrupt > property (Rob Herring). > > Changes in v4: > - Add link to bridge chip datasheet (Stephen Boyd) > - Add vpll and vcc regulator supply bindings (Stephen Boyd) > - Add ref clk optional dt binding (Stephen Boyd) > - Add gpio-controller optional dt binding (Stephen Boyd) > > Changes in v5: > - Use clock property to specify the input refclk (Stephen Boyd). > - Update gpio cell and pwm cell numbers (Stephen Boyd). > > Changes in v6: > - Add property to mention the lane mapping scheme and polarity inversion > (Stephen Boyd). > > Changes in v7: > - Detail description of lane mapping scheme dt property (Andrzej > Hajda/ Rob Herring). > - Removed HDP gpio binding, since the bridge uses IRQ signal to > determine HPD, and IRQ property is already documented in binding. > > Changes in v8: > - Removed unnecessary explanation of lane mapping and polarity dt > property, since these are already explained in media/video-interface > dt binidng (Rob Herring). > > Signed-off-by: Sandeep Panda <spanda@xxxxxxxxxxxxxx> > --- > .../bindings/display/bridge/ti,sn65dsi86.txt | 90 ++++++++++++++++++++++ > 1 file changed, 90 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt > > diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt > new file mode 100644 > index 0000000..601454c > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt > @@ -0,0 +1,90 @@ > +SN65DSI86 DSI to eDP bridge chip > +-------------------------------- > + > +This is the binding for Texas Instruments SN65DSI86 bridge. > +http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf > + > +Required properties: > +- compatible: Must be "ti,sn65dsi86" > +- reg: i2c address of the chip, 0x2d as per datasheet > +- enable-gpios: OF device-tree gpio specification for bridge_en pin (active high) > + > +- vccio-supply: A 1.8V supply that powers up the digital IOs. > +- vpll-supply: A 1.8V supply that powers up the displayport PLL. > +- vcca-supply: A 1.2V supply that powers up the analog circuits. > +- vcc-supply: A 1.2V supply that powers up the digital core. > + > +Optional properties: > +- interrupts: Specifier for the SN65DSI86 interrupt line. > + > +- ddc-i2c-bus: phandle of the I2C controller used for DDC EDID probing > + > +- gpio-controller: Marks the device has a GPIO controller. > +- #gpio-cells : Should be two. The first cell is the pin number and > + the second cell is used to specify flags. > + See ../../gpio/gpio.txt for more information. > +- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description of > + the cell formats. > + > +- clock-names: should be "refclk" > +- clocks: Specification for input reference clock. The reference > + clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz. > + > +- data-lanes: Specification to describe the logical to physical lane > + mapping scheme. See ../../media/video-interface.txt for more > + information. > +- lane-polarities: Specification to describe the polarity of physical lanes. > + See ../../media/video-interface.txt for more information. You are still defining the properties here. All you need is: data-lanes: See ../../media/video-interface.txt Perhaps you need to say should be 4 lanes, but OTOH everything tends to be 4 lanes. Rob _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
