Am Dienstag, den 30.01.2018, 21:29 +0100 schrieb Thierry Escande:
> From: Sean Paul <seanpaul@xxxxxxxxxxxx>
>
> Change the mode for Sharp lq123p1jx31 panel to something more
> rockchip-friendly such that we can use the fixed PLLs to
> generate the pixel clock
This should really switch to a display timing instead of exposing a
single mode. The display timing has min, typical, max tuples for all
the timings values, which would allow the attached driver to vary the
timings inside the allowed bounds if it makes sense.
Trying to hit a specific pixel clock to free up a PLL is exactly one of
the use cases envisioned for the display timings stuff.
Regards,
Lucas
> Cc: Chris Zhong <zyw@xxxxxxxxxxxxxx>
> Cc: Stéphane Marchesin <marcheu@xxxxxxxxxxxx>
> Signed-off-by: Sean Paul <seanpaul@xxxxxxxxxxxx>
> Signed-off-by: Thierry Escande <thierry.escande@xxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/panel/panel-simple.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c
> b/drivers/gpu/drm/panel/panel-simple.c
> index 5591984a392b..a4a6ea3ca0e6 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -1742,17 +1742,18 @@ static const struct panel_desc
> sharp_lq101k1ly04 = {
> };
>
> static const struct drm_display_mode sharp_lq123p1jx31_mode = {
> - .clock = 252750,
> + .clock = 266667,
> .hdisplay = 2400,
> .hsync_start = 2400 + 48,
> .hsync_end = 2400 + 48 + 32,
> - .htotal = 2400 + 48 + 32 + 80,
> + .htotal = 2400 + 48 + 32 + 139,
> .vdisplay = 1600,
> .vsync_start = 1600 + 3,
> .vsync_end = 1600 + 3 + 10,
> - .vtotal = 1600 + 3 + 10 + 33,
> + .vtotal = 1600 + 3 + 10 + 84,
> .vrefresh = 60,
> .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
> + .type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER,
> };
>
> static const struct panel_desc sharp_lq123p1jx31 = {
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