On 03.11.2017 18:01, Andrey Gusakov wrote:
> Minimum pixel clock period is 6.5 nS for DPI. Do not accept modes
> with lower pixel clock period.
> ---
> drivers/gpu/drm/bridge/tc358767.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index d52cd41..7f9c2e0 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -1103,7 +1103,10 @@ static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
> static int tc_connector_mode_valid(struct drm_connector *connector,
> struct drm_display_mode *mode)
> {
> - /* Accept any mode */
> + /* PCLK limitation = 6.5 nS */
> + if (mode->clock > 154000)
> + return MODE_CLOCK_HIGH;
> +
>From Datasheet I've found, and your response in v1 it looks like
Datasheet defines the limit as "154 MPs (MPixel per sec)",
so let's remove 6.5nS from comment and description (if there will be
next patchset iteration, or quick fix).
This is not blocking issue so:
Reviewed-by: Andrzej Hajda <a.hajda@xxxxxxxxxxx>
--
Regards
Andrzej
> return MODE_OK;
> }
>
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