[PATCH] drm/radeon/kms: use DIG*EncoderControl for DP link training on all generation

[j.glisse@xxxxxxxxx]

From: Jerome Glisse <jglisse@xxxxxxxxxx>

atombios functuion DIG*EncoderControl works more reliably (100% link training
success vs 30% link training success on some monitor like HP ZR22w) for DP link
training than DPEncoderService for DCE3 display block.

Signed-off-by: Jerome Glisse <jglisse@xxxxxxxxxx>
---
 drivers/gpu/drm/radeon/atombios_dp.c |   52 ++++++++++------------------------
 1 files changed, 15 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 8c0f9e3..9093e5e 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -645,32 +645,18 @@ static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
 {
 	int rtp = 0;
 
-	/* set training pattern on the source */
-	if (ASIC_IS_DCE4(dp_info->rdev)) {
-		switch (tp) {
-		case DP_TRAINING_PATTERN_1:
-			rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
-			break;
-		case DP_TRAINING_PATTERN_2:
-			rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
-			break;
-		case DP_TRAINING_PATTERN_3:
-			rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
-			break;
-		}
-		atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
-	} else {
-		switch (tp) {
-		case DP_TRAINING_PATTERN_1:
-			rtp = 0;
-			break;
-		case DP_TRAINING_PATTERN_2:
-			rtp = 1;
-			break;
-		}
-		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
-					  dp_info->dp_clock, dp_info->enc_id, rtp);
+	switch (tp) {
+	case DP_TRAINING_PATTERN_1:
+		rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
+		break;
+	case DP_TRAINING_PATTERN_2:
+		rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
+		break;
+	case DP_TRAINING_PATTERN_3:
+		rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
+		break;
 	}
+	atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
 
 	/* enable training pattern on the sink */
 	radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
@@ -706,12 +692,8 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 	radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
 
 	/* start training on the source */
-	if (ASIC_IS_DCE4(dp_info->rdev))
-		atombios_dig_encoder_setup(dp_info->encoder,
-					   ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
-	else
-		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
-					  dp_info->dp_clock, dp_info->enc_id, 0);
+	atombios_dig_encoder_setup(dp_info->encoder,
+				ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 
 	/* disable the training pattern on the sink */
 	radeon_write_dpcd_reg(dp_info->radeon_connector,
@@ -731,12 +713,8 @@ static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info
 			      DP_TRAINING_PATTERN_DISABLE);
 
 	/* disable the training pattern on the source */
-	if (ASIC_IS_DCE4(dp_info->rdev))
-		atombios_dig_encoder_setup(dp_info->encoder,
-					   ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
-	else
-		radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
-					  dp_info->dp_clock, dp_info->enc_id, 0);
+	atombios_dig_encoder_setup(dp_info->encoder,
+				ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 
 	return 0;
 }
-- 
1.7.1

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