[bug report] drm/amd/powerplay: implement smu7 hwmgr to manager asics with smu ip version 7.

[Dan Carpenter <dan.carpenter@xxxxxxxxxx>]

Hello Rex Zhu,

The patch 599a7e9fe1b6: "drm/amd/powerplay: implement smu7 hwmgr to
manager asics with smu ip version 7." from Sep 9, 2016, leads to the
following static checker warning:

	drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c:2125 smu7_patch_limits_vddc()
	warn: passing casted pointer '&tab->vddc' to 'smu7_patch_ppt_v0_with_vdd_leakage()' 16 vs 32.

drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_hwmgr.c
  2119  static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
  2120                                       struct phm_clock_and_voltage_limits *tab)
  2121  {
  2122          struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
  2123  
  2124          if (tab) {
  2125                  smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, (uint32_t *)&tab->vddc,
  2126                                                          &data->vddc_leakage);

This call corrupts vddci.

  2127                  smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, (uint32_t *)&tab->vddci,
  2128                                                          &data->vddci_leakage);

But that's fine since we immediately overwrite it here.  But
unfortunately this call corrupt tab->vddgfx.

  2129          }
  2130  
  2131          return 0;
  2132  }

regards,
dan carpenter
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