On Wed, Jun 8, 2011 at 11:31 AM, Meelis Roos <mroos@xxxxxxxx> wrote:
>> > I have LG Flatron F900P CRT monitor. X drivers work fine, nouveau KMS
>> > works fine but Radeon KMS selects a videomode that is out of spec for
>> > monitor. This is not a regression - this hardware combination has never
>> > worked for me yet with radeon KMS. The result is same for Radeon 7000
>> > (RV100, currently installed) and Radeon 9200 series card.
>
> Umm, I guess I forgot one important aspect. When X comes up, it finds a
> good video mode and gets a picture. It's just the text consoles that
> have no picture.
>
> In the console, it tells it's using 352x132 console. This translates
> with 8x16 font to 2816x2112 and 9x16 font to 3168x2112 if I calculated
> the right thing.
>
> Running fbset remotely verifies this:
>
> # fbset -s </dev/tty1
>
> mode "2816x2114"
> geometry 2816 2114 2816 2114 8
> timings 0 0 0 0 0 0 0
> accel true
> rgba 8/0,8/0,8/0,0/0
> endmode
>
> So it decides this modeline is usable for the console while it is not.
>
Ah, ok. yeah, that mode has a much higher clock than those chips can
handle. Where is that mode even coming from? I don't see it in the
EDID. The attached patch should filter out that mode.
Alex
From 890626ca18f9dec7ed49a4122153894a08689b4a Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@xxxxxxxxx>
Date: Wed, 8 Jun 2011 12:53:53 -0400
Subject: [PATCH] drm/radeon/kms: check modes against max pixel clock
Filter out modes that are higher than the max pixel
clock.
Signed-off-by: Alex Deucher <alexdeucher@xxxxxxxxx>
---
drivers/gpu/drm/radeon/radeon.h | 1 +
drivers/gpu/drm/radeon/radeon_atombios.c | 4 ++++
drivers/gpu/drm/radeon/radeon_clocks.c | 8 +++++---
drivers/gpu/drm/radeon/radeon_combios.c | 5 +++++
drivers/gpu/drm/radeon/radeon_connectors.c | 13 ++++++++++++-
5 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 625f1af..bbcb00a 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -165,6 +165,7 @@ struct radeon_clock {
uint32_t default_sclk;
uint32_t default_dispclk;
uint32_t dp_extclk;
+ uint32_t max_pixel_clock;
};
/*
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 90dfb2b..fa62a50 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1246,6 +1246,10 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
}
*dcpll = *p1pll;
+ rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
+ if (rdev->clock.max_pixel_clock == 0)
+ rdev->clock.max_pixel_clock = 40000;
+
return true;
}
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index 5249af8..2d48e7a 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -117,7 +117,7 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
if (p1pll->reference_div < 2)
p1pll->reference_div = 12;
- p2pll->reference_div = p1pll->reference_div;
+ p2pll->reference_div = p1pll->reference_div;
/* These aren't in the device-tree */
if (rdev->family >= CHIP_R420) {
@@ -139,6 +139,8 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
p2pll->pll_out_min = 12500;
p2pll->pll_out_max = 35000;
}
+ /* not sure what the max should be in all cases */
+ rdev->clock.max_pixel_clock = 35000;
spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
spll->reference_div = mpll->reference_div =
@@ -151,7 +153,7 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
else
rdev->clock.default_sclk =
radeon_legacy_get_engine_clock(rdev);
-
+
val = of_get_property(dp, "ATY,MCLK", NULL);
if (val && *val)
rdev->clock.default_mclk = (*val) / 10;
@@ -160,7 +162,7 @@ static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
radeon_legacy_get_memory_clock(rdev);
DRM_INFO("Using device-tree clock info\n");
-
+
return true;
}
#else
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 19b10cf..797c8bc 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -866,6 +866,11 @@ bool radeon_combios_get_clock_info(struct drm_device *dev)
rdev->clock.default_sclk = sclk;
rdev->clock.default_mclk = mclk;
+ if (RBIOS32(pll_info + 0x16))
+ rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
+ else
+ rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
+
return true;
}
return false;
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 9dc8684..1d1504b 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -628,8 +628,14 @@ static int radeon_vga_get_modes(struct drm_connector *connector)
static int radeon_vga_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
+ struct drm_device *dev = connector->dev;
+ struct radeon_device *rdev = dev->dev_private;
+
/* XXX check mode bandwidth */
- /* XXX verify against max DAC output frequency */
+
+ if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
+ return MODE_CLOCK_HIGH;
+
return MODE_OK;
}
@@ -1017,6 +1023,11 @@ static int radeon_dvi_mode_valid(struct drm_connector *connector,
} else
return MODE_CLOCK_HIGH;
}
+
+ /* check against the max pixel clock */
+ if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
+ return MODE_CLOCK_HIGH;
+
return MODE_OK;
}
--
1.7.1.1
_______________________________________________
dri-devel mailing list
dri-devel@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/dri-devel
