On Fri, Jul 15, 2016 at 06:13:56PM -0400, Lyude wrote: > At long last, the time has finally come for Skylake users to plug their > external displays back in. > > During intel_atomic_commit() on Skylake, we've actually been arming the > registers to update the cursor information twice instead of just once. > Once in i9xx_update_cursor(), and once in skl_wm_flush_pipe(). This > isn't actually necessary, and removing the later update in > skl_wm_flush_pipe() has completely stopped the underruns on this T460p > from occurring when moving the mouse cursor from one monitor to another. > > Signed-off-by: Lyude <cpaul@xxxxxxxxxx> > Cc: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx> > Cc: Hans de Goede <hdegoede@xxxxxxxxxx> > Cc: stable@xxxxxxxxxxxxxxx > --- > drivers/gpu/drm/i915/intel_pm.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 7ac71ec..4771a03 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3860,7 +3860,6 @@ skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) > I915_WRITE(PLANE_SURF(pipe, plane), > I915_READ(PLANE_SURF(pipe, plane))); > } > - I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); The WM/BUF_CFG register double buffering is armed by the plane surface register, so if you're removing this write, all you actually end up doing is skipping the watermark update. So this is just papering over the bug. This might even cause more explosions when enabling pipes, as the DDB configuration for the cursors on the already enabled pipes might not even get updated, and hence multiple planes migth end up trying to use the same part of the DDB for their FIFOs. -- Ville Syrjälä Intel OTC _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
