On 04/04, Stefan Agner wrote: > Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy > mixes the bus clock with the display controllers pixel clock. Tests > have shown that the gates in CCM_CCGR3/9 registers do not control > the DCU pixel clock, but only the register access clock (bus clock). > > Fix this by defining the parent clock of VF610_CLK_DCUx to be the bus > clock (ipg_bus). > > Since the clock has not been used far, there are no further changes > needed. > > Signed-off-by: Stefan Agner <stefan@xxxxxxxx> > --- Acked-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx> -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/dri-devel
