On Sat, 26 Mar 2016, Paul Parsons <lost.distance@xxxxxxxxx> wrote:
> The EDID 1.4 specification section 3.10.3.9 defines an Established Timings III
> descriptor (tag #F7h). The parsing of this descriptor by drm_est3_modes() is
> off by one byte: the offset of the first timing bitmap is 6, not 5.
>
> Signed-off-by: Paul Parsons <lost.distance@xxxxxxxxx>
I'm not all that familiar with the EDID parsing code, but this seems
right.
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
I'd appreciate an extra set of eyeballs on this one still.
Makes you wonder about the implications though. We've been reading the
revision number as a bitmask and otherwise been off by one byte. The
interpretation of Established Timings III would have been pretty much
random. Where are the bugs?
BR,
Jani.
> ---
>
> diff -ru a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> --- a/drivers/gpu/drm/drm_edid.c 2016-03-14 04:28:54.000000000 +0000
> +++ b/drivers/gpu/drm/drm_edid.c 2016-03-26 12:04:58.963352156 +0000
> @@ -2215,7 +2215,7 @@
> {
> int i, j, m, modes = 0;
> struct drm_display_mode *mode;
> - u8 *est = ((u8 *)timing) + 5;
> + u8 *est = ((u8 *)timing) + 6;
>
> for (i = 0; i < 6; i++) {
> for (j = 7; j >= 0; j--) {
>
>
>
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--
Jani Nikula, Intel Open Source Technology Center
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