On 11/6/24 10:48 AM, Pandey, Radhey Shyam wrote:
-----Original Message-----
From: Marek Vasut <marex@xxxxxxx>
Sent: Thursday, October 31, 2024 10:28 PM
To: dmaengine@xxxxxxxxxxxxxxx
Cc: Marek Vasut <marex@xxxxxxx>; Uwe Kleine-König <u.kleine-
koenig@xxxxxxxxxxxx>; Simek, Michal <michal.simek@xxxxxxx>; Peter Korsgaard
<peter@xxxxxxxxxxxxx>; Pandey, Radhey Shyam
<radhey.shyam.pandey@xxxxxxx>; Vinod Koul <vkoul@xxxxxxxxxx>; linux-arm-
kernel@xxxxxxxxxxxxxxxxxxx
Subject: [PATCH] dmaengine: xilinx_dma: Fix freeup active list based on descriptor
completion bit
The xilinx_dma is completely broken since the referenced commit,
because if the (seg->hw.status & XILINX_DMA_BD_COMP_MASK) is not
set for whatever reason, the current descriptor is never moved to
I want to understand more on this failure scenario. How to replicate it?
The very basic test is to use AXI DMA for DMA transfer, which fails to
complete because of this new chunk of code. By reading the commit
history, I can only conclude this was something that got added due to
the irq_delay, but was never tested on core without irq_delay support ?
Why is completion bit not set ? Based on the documentation completed bit
indicates to the software that the DMA Engine has completed the transfer
as described by the associated descriptor. The DMA Engine sets this bit
to 1 when the transfer is completed.
I don't know, the bit was not used before you added the bit and check of
the bit in the problematic commit 7bcdaa658102 ("dmaengine: xilinx_dma:
Freeup active list based on descriptor completion bit")
