Hi JiaJie On 12-06-24, 10:13, JiaJie Ho wrote: > > On 30-05-24, 11:11, Jia Jie Ho wrote: > > > > > + > > > +struct dw_axi_peripheral_config { > > > +#define DWAXIDMAC_STARFIVE_SM_ALGO BIT(0) > > > > what does this quirk mean? > > > > > + u32 quirks; > > > > Can you explain why you need this to be exposed. I would prefer we use > > existing interfaces and not define a new one... > > > > Hi Vinod, > Thanks for reviewing this. > This is a dedicated dma controller for the crypto engine. > I am adding this quirk to: > 1. Select the src and dest AXI master for transfers between mem and dev. > Driver currently only uses AXI0 for both. why cant this information be passed thru DT, that is typically done by most controllers? > 2. Workaround a hardware limitation on the crypto engine to > transfer data > 256B by incrementing the peripheral FIFO offset. Dont set the transfer data > 256B, you should ideally use maxburst for configuring the FIFO... > > What is the recommended way to handle such cases besides using > peripheral_config in dma_slave_config? First use dma_slave_config() fields, if they are not appropriate, lets discuss why before we add custom methods or use peripheral_config -- ~Vinod