On Sat, 23 Mar 2024 11:34:53 -0400, Frank Li wrote: > From: Joy Zou <joy.zou@xxxxxxx> > > Introduce the compatible string 'fsl,imx8ulp-edma' to enable support for > the i.MX8ULP's eDMA, alongside adjusting the clock numbering. The i.MX8ULP > eDMA architecture features one clock for each DMA channel and an additional > clock for the core controller. Given a maximum of 32 DMA channels, the > maximum clock number consequently increases to 33. > > Signed-off-by: Joy Zou <joy.zou@xxxxxxx> > Signed-off-by: Frank Li <Frank.Li@xxxxxxx> > --- > > Notes: > Changes in v3: > - Change clock name form CHXX-CLK to chxx > - Fix typeo 'clock' > - Add dma-cell description > - About clock-names: > items: > oneOf: > - const: dma > - pattern: ... > > Which already detect naming wrong, for example: > > clock-names = "dma", "ch00", "ch01", "ch02", "ch03", > .... > "ch28", "ch29", "ch30", "abcc"; > > arch/arm64/boot/dts/freescale/imx8ulp-evk.dtb: dma-controller@29010000: clock-names:32: 'oneOf' conditional failed, one must be fixed: > 'dma' was expected > 'abcc' does not match '^ch(0[0-9]|[1-2][0-9]|3[01])$' > > Only lose order check, such as ch00, dma, ch03, ch02, can pass check. > I think it is good enough. > > I tried rob's suggestion, but met some technology issue. Detail see > > https://lore.kernel.org/imx/20240229-8ulp_edma-v2-0-9d12f883c8f7@xxxxxxx/T/#mc5767dd505d4b7cfc66586a0631684a57e735476 > > .../devicetree/bindings/dma/fsl,edma.yaml | 40 ++++++++++++++++++++-- > 1 file changed, 38 insertions(+), 2 deletions(-) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
