On Mon, 18 Dec 2023 12:39:04 +0100, Jan Kuliga wrote:
> This patchset introduces a couple of xdma driver enhancements. The most
> important change is the introduction of interleaved DMA transfers
> feature, which is a big deal, as it allows DMAEngine clients to express
> DMA transfers in an arbitrary way. This is extremely useful in FPGA
> environments, where in one FPGA system there may be a need to do DMA both
> to/from FIFO at a fixed address and to/from a (non)contiguous RAM.
>
> [...]
Applied, thanks!
[1/8] dmaengine: xilinx: xdma: Get rid of unused code
commit: 6e2387183312cdfce6326b2626c0b801c2ffe686
[2/8] dmaengine: xilinx: xdma: Add necessary macro definitions
commit: 7a9c7f46bd0abea214d96f00f78622f24c798ad8
[3/8] dmaengine: xilinx: xdma: Ease dma_pool alignment requirements
commit: e5bc76b0e1c54906ca744ed1a7872f4f407d5d2e
[4/8] dmaengine: xilinx: xdma: Rework xdma_terminate_all()
commit: 2e142cebb1645ac18db1e66f0c30a8d720d00c0b
[5/8] dmaengine: xilinx: xdma: Add error checking in xdma_channel_isr()
commit: c38d055a7c021145ab3a07cf69992d287440c4cb
[6/8] dmaengine: xilinx: xdma: Add transfer error reporting
commit: c3fcb6f5575fcfd240baa339319d2a42d137cd8e
[7/8] dmaengine: xilinx: xdma: Prepare the introduction of interleaved DMA transfers
commit: fa88abfd0d03fea8b800ff1df4f161c804d24c8a
[8/8] dmaengine: xilinx: xdma: Implement interleaved DMA transfers
commit: 01e6d907656134949c4126e7fd64984d4daa4c1e
Best regards,
--
~Vinod
