> From: Jacob Pan <jacob.jun.pan@xxxxxxxxxxxxxxx>
> Sent: Friday, April 28, 2023 1:50 AM
>
> Devices that use Intel ENQCMD to submit work must use global PASIDs in
> that the PASID are stored in a per CPU MSR. When such device need to
> submit work for in-kernel DMA with PASID, it must allocate PASIDs from
> the same global number space to avoid conflict.
well the device itself cannot submit work to itself. It's software to
submit work to the device. 😊
> /* Allocate a PASID for the mm within range (inclusive) */
> -static int iommu_sva_alloc_pasid(struct mm_struct *mm, ioasid_t min,
> ioasid_t max)
> +static int iommu_sva_alloc_pasid(struct mm_struct *mm, struct device *dev)
> {
> int ret = 0;
>
> - if (!pasid_valid(min) || !pasid_valid(max) ||
> - min == 0 || max < min)
> - return -EINVAL;
> -
> mutex_lock(&iommu_sva_lock);
> /* Is a PASID already associated with this mm? */
> - if (pasid_valid(mm->pasid)) {
> - if (mm->pasid < min || mm->pasid > max)
> - ret = -EOVERFLOW;
> + if (pasid_valid(mm->pasid))
> goto out;
emmm here you still want to check whether mm->pasid exceeds
the max pasid width of the bound device.
