On 10-06-22, 12:14, Serge Semin wrote: > This is a final patchset in the series created in the framework of > my Baikal-T1 PCIe/eDMA-related work: > > [1: In-progress v4] PCI: dwc: Various fixes and cleanups > Link: https://lore.kernel.org/linux-pci/20220610082535.12802-1-Sergey.Semin@xxxxxxxxxxxxxxxxxxxx/ > [2: In-progress v3] PCI: dwc: Add hw version and dma-ranges support > Link: https://lore.kernel.org/linux-pci/20220610084444.14549-1-Sergey.Semin@xxxxxxxxxxxxxxxxxxxx/ > [3: In-progress v3] PCI: dwc: Add generic resources and Baikal-T1 support > Link: https://lore.kernel.org/linux-pci/20220610085706.15741-1-Sergey.Semin@xxxxxxxxxxxxxxxxxxxx/ > [4: In-progress v3] dmaengine: dw-edma: Add RP/EP local DMA support > Link: ---you are looking at it--- > > Note it is very recommended to merge the patchsets in the same order as > they are listed in the set above in order to have them applied smoothly. > Nothing prevents them from being reviewed synchronously though. > > Please note originally this series was self content, but due to Frank > being a bit faster in his work submission I had to rebase my patchset onto > his one. So now this patchset turns to be dependent on the Frank' work: > > Link: https://lore.kernel.org/linux-pci/20220524152159.2370739-1-Frank.Li@xxxxxxx/ > > So please merge Frank' series first before applying this one. > > Here is a short summary regarding this patchset. The series starts with > fixes patches. We discovered that the dw-edma-pcie.c driver incorrectly > initializes the LL/DT base addresses for the platforms with not matching > CPU and PCIe memory spaces. It is fixed by using the pci_bus_address() > method to get a correct base address. After that you can find a series of > the interleaved xfers fixes. It turned out the interleaved transfers > implementation didn't work quite correctly from the very beginning for > instance missing src/dst addresses initialization, etc. In the framework > of the next two patches we suggest to add a new platform-specific > callback - pci_address() and use it to convert the CPU address to the PCIe > space address. It is at least required for the DW eDMA remote End-point > setup on the platforms with not-matching CPU/PCIe address spaces. In case > of the DW eDMA local RP/EP setup the conversion will be done automatically > by the outbound iATU (if no DMA-bypass flag is specified for the > corresponding iATU window). Then we introduce a set of the patches to make > the DebugFS part of the code supporting the multi-eDMA controllers > platforms. It starts with several cleanup patches and is closed joining > the Read/Write channels into a single DMA-device as they originally should > have been. After that you can find the patches with adding the non-atomic > io-64 methods usage, dropping DT-region descriptors allocation, replacing > chip IDs with the device name. In addition to that in order to have the > eDMA embedded into the DW PCIe RP/EP supported we need to bypass the > dma-ranges-based memory ranges mapping since in case of the root port DT > node it's applicable for the peripheral PCIe devices only. Finally at the > series closure we introduce a generic DW eDMA controller support being > available in the DW PCIe Root Port/Endpoint driver. Acked-By: Vinod Koul <vkoul@xxxxxxxxxx> -- ~Vinod
