On 13-01-21, 15:05, Andy Shevchenko wrote: > On Wed, Jan 13, 2021 at 5:23 AM Ferry Toth <ftoth@xxxxxxxxxxxxxx> wrote: > > > > On Intel Tangier B0 and Anniedale the interrupt line, disregarding > > to have different numbers, is shared between HSU DMA and UART IPs. > > Thus on such SoCs we are expecting that IRQ handler is called in > > UART driver only. hsu_pci_irq was handling the spurious interrupt > > hsu_pci_irq() > > > from HSU DMA by returning immediately. This wastes CPU time and > > since HSU DMA and HSU UART interrupt occur simultaneously they race > > to be handled causing delay to the HSU UART interrupt handling. > > Fix this by disabling the interrupt entirely. > > Title should be "dmaengine: hsu: ..." Fixed that up while applying, so applied -- ~Vinod
