Hi Vinod,
Thank for you reply.
the registers (CHCFG0 - CHCFG15) on big endian socs as fallows:
CHCFG0 0x0
CHCFG1 0x1
CHCFG2 0x2
CHCFG3 0x3
......
CHCFG12 0xC
CHCFG13 0xD
CHCFG14 0xE
CHCFG15 0xF
On little endian socs as fallows:
CHCFG3 0x0
CHCFG2 0x1
CHCFG1 0x2
CHCFG0 0x3
......
CHCFG15 0xC
CHCFG14 0xD
CHCFG13 0xE
CHCFG12 0xF
To fit this map we should add this patch.
Best Regards,
Peng
>-----Original Message-----
>From: Vinod Koul <vkoul@xxxxxxxxxx>
>Sent: 2019年5月21日 12:38
>To: Peng Ma <peng.ma@xxxxxxx>
>Cc: robh+dt@xxxxxxxxxx; shawnguo@xxxxxxxxxx; mark.rutland@xxxxxxx; Leo
>Li <leoyang.li@xxxxxxx>; dan.j.williams@xxxxxxxxx;
>dmaengine@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
>linux-kernel@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
>Subject: [EXT] Re: [PATCH 3/4] dmaengine: fsl-edma: support little endian for
>edma driver
>
>Caution: EXT Email
>
>On 06-05-19, 09:03, Peng Ma wrote:
>> improve edma driver to support little endian.
>
>Can you explain a bit more how adding the below lines adds little endian
>support...
>
>>
>> Signed-off-by: Peng Ma <peng.ma@xxxxxxx>
>> ---
>> drivers/dma/fsl-edma-common.c | 5 +++++
>> 1 files changed, 5 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/dma/fsl-edma-common.c
>> b/drivers/dma/fsl-edma-common.c index 680b2a0..6bf238e 100644
>> --- a/drivers/dma/fsl-edma-common.c
>> +++ b/drivers/dma/fsl-edma-common.c
>> @@ -83,9 +83,14 @@ void fsl_edma_chan_mux(struct fsl_edma_chan
>*fsl_chan,
>> u32 ch = fsl_chan->vchan.chan.chan_id;
>> void __iomem *muxaddr;
>> unsigned int chans_per_mux, ch_off;
>> + int endian_diff[4] = {3, 1, -1, -3};
>>
>> chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR;
>> ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
>> +
>> + if (!fsl_chan->edma->big_endian)
>> + ch_off += endian_diff[ch_off % 4];
>> +
>> muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
>> slot = EDMAMUX_CHCFG_SOURCE(slot);
>>
>> --
>> 1.7.1
>
>--
>~Vinod
