On 16-05-19, 10:04, Alexandru Ardelean wrote: > From: Dragos Bogdan <dragos.bogdan@xxxxxxxxxx> > > The DMAC HDL core supports interleaved & cyclic transfers. > An example use-case for this mode is when the controller is used as a > video DMA. > > This change sets the `cyclic` field to true, so that when the IRQ comes and > the `axi_dmac_transfer_done()` callback is called (from the interrupt > handler) the proper `vchan_cyclic_callback()` is called. This way the > DMAEngine framework will process data correctly for interleaved + cyclic > transfers. > > This doesn't fix anything. It's an enhancement to the driver. Applied, thanks -- ~Vinod
