From: Dragos Bogdan <dragos.bogdan@xxxxxxxxxx> The DMAC HDL core supports interleaved & cyclic transfers. An example use-case for this mode is when the controller is used as a video DMA. This change sets the `cyclic` field to true, so that when the IRQ comes and the `axi_dmac_transfer_done()` callback is called (from the interrupt handler) the proper `vchan_cyclic_callback()` is called. This way the DMAEngine framework will process data correctly for interleaved + cyclic transfers. This doesn't fix anything. It's an enhancement to the driver. Signed-off-by: Dragos Bogdan <dragos.bogdan@xxxxxxxxxx> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@xxxxxxxxxx> --- drivers/dma/dma-axi-dmac.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c index f32fdf21edbd..4d2cae0bebb5 100644 --- a/drivers/dma/dma-axi-dmac.c +++ b/drivers/dma/dma-axi-dmac.c @@ -562,6 +562,9 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_interleaved( desc->sg[0].y_len = 1; } + if (flags & DMA_CYCLIC) + desc->cyclic = true; + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); } -- 2.17.1
