Re: [PATCH 2/2] dma: xilinx: Add driver for Video Framebuffer IP

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Hi Vinod,

On 20.12.2017 18:05, Vinod Koul wrote:
> On Wed, Dec 20, 2017 at 02:00:18PM +0530, Vishal Sagar wrote:
>> The Video Framebuffer IP is available in two forms: read or write.
>> This driver supports either form of the IP.
>> Each IP is a single channel DMA and is video format aware.
>> It can read/write video data arranged from/to memory as packed or
>> semi-planar way based on the selected video format.
>> To get list of supported video formats, clients can call certain
>> APIs exposed by the driver. This driver introduces support for
>> these IPs and integrates with the DMA Engine Framework.
> 
> The subsytem name is dmaengine!
> 
>> Signed-off-by: Radhey Shyam Pandey <radheys@xxxxxxxxxx>
>> Signed-off-by: John Nichols <jnichol@xxxxxxxxxx>
>> Signed-off-by: Jeffrey Mouroux <jmouroux@xxxxxxxxxx>
>> Signed-off-by: Michal Simek <michal.simek@xxxxxxxxxx>
>> Signed-off-by: Hyun Kwon <hyun.kwon@xxxxxxxxxx>
>> Signed-off-by: Vishal Sagar <vsagar@xxxxxxxxxx>
>> ---
>>  drivers/dma/Kconfig                |   14 +-
>>  drivers/dma/xilinx/Makefile        |    1 +
>>  drivers/dma/xilinx/xilinx_frmbuf.c | 1155 ++++++++++++++++++++++++++++++++++++
> 
> Thats a very large file for review, do consider splitting stuff
> 
>> @@ -342,7 +342,7 @@ config MOXART_DMA
>>  	select DMA_VIRTUAL_CHANNELS
>>  	help
>>  	  Enable support for the MOXA ART SoC DMA controller.
>> -
>> +
> 
> why this noise, this patch has some many sign-off's but didnt anyone see this
> noise?
> 
>> +// SPDX-License-Identifier: GPL-2.0
> 
> Copyright needs to follow this in C99 style
> 
>> +/*
>> + * DMAEngine driver for Xilinx Framebuffer IP
>> + *
>> + * Copyright (C) 2016 - 2017 Xilinx, Inc. All rights reserved.
>> + *
>> + * Authors: Radhey Shyam Pandey <radheys@xxxxxxxxxx>
>> + *          John Nichols <jnichol@xxxxxxxxxx>
>> + *          Jeffrey Mouroux <jmouroux@xxxxxxxxxx>
>> + *
>> + * Based on the Freescale DMA driver.
>> + *
>> + * Description:
>> + * The AXI Framebuffer core is a soft Xilinx IP core that
>> + * provides high-bandwidth direct memory access between memory
>> + * and AXI4-Stream.
>> + *
>> + * This program is free software: you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation, either version 2 of the License, or
>> + * (at your option) any later version.
> 
> why do you need this license text? With SPDX tag this is implied..

We are in touch with Xilinx Legal to clear this if SPDX is enough.
We have been discussing this recently here.
https://lkml.org/lkml/2017/12/18/112

I will let you know when we have this discussion done. Right now I have
recommended to add SPDX header and also license text fragment which was
present in driver version added to Xilinx git tree.

Thanks,
Michal
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